339 lines
9.7 KiB
VHDL
339 lines
9.7 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.MATH_REAL.all;
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library work;
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use work.socbridge_driver_tb_pkg.all;
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library ganimede;
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use ganimede.io_types.all;
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entity socbridge_driver_tb is
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end entity socbridge_driver_tb;
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architecture tb of socbridge_driver_tb is
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signal clk : std_logic := '0';
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signal rst : std_logic;
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signal cmd : command_t;
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signal address : std_logic_vector(31 downto 0);
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signal cmd_size : positive;
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signal ext_in : ext_socbridge_in_t;
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signal ext_out : ext_socbridge_out_t;
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signal int_in : int_socbridge_in_t;
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signal int_out : int_socbridge_out_t;
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signal curr_word : std_logic_vector(ext_in.payload'length - 1 downto 0);
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signal expected_out : std_logic_vector(ext_out.payload'length - 1 downto 0);
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constant CLK_PERIOD : TIME := 10 ns;
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constant SIMULATION_CYCLE_COUNT : INTEGER := 100;
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procedure fail(error_msg : string) is
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begin
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wait for CLK_PERIOD;
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report "Simulation ending due to: " & error_msg & ". Shutting down..." severity FAILURE;
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end procedure;
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procedure check_next_state(correct_state: state_t) is
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begin
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if(not (correct_state = G_next_state)) then
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report "Next State is not what was expected, found " & state_t'image(G_next_state)
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& " but expected " & state_t'image(correct_state) severity error;
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fail("Next State");
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end if;
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end procedure;
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procedure check_data_out(correct_data: std_logic_vector(ext_out.payload'length - 1 downto 0)) is
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begin
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if(not (correct_data = ext_out.payload)) then
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report "Data out is not what was expected, found " & to_string(ext_out.payload)
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& " but expected " & to_string(correct_data) severity error;
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fail("Data out");
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end if;
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end procedure;
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procedure check_parity(correct_data: std_logic_vector(ext_out.payload'length - 1 downto 0)) is
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begin
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if(not (calc_parity(correct_data) = calc_parity(ext_out.payload))) then
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report "Parity out is not what was expected, found " & std_logic'image(calc_parity(ext_out.payload))
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& " but expected " & std_logic'image(calc_parity(correct_data)) severity error;
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fail("Parity out");
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end if;
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end procedure;
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component socbridge_driver is
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port(
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clk : in std_logic;
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rst : in std_logic;
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cmd : in command_t;
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address : in std_logic_vector(31 downto 0);
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cmd_size: in positive;
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ext_in : in ext_socbridge_in_t;
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ext_out : out ext_socbridge_out_t;
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int_in : out int_socbridge_in_t;
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int_out : in int_socbridge_out_t
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);
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end component socbridge_driver;
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begin
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socbridge_driver_inst: entity work.socbridge_driver
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port map(
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clk => clk,
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rst => rst,
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cmd => cmd,
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address => address,
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cmd_size => cmd_size,
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ext_in => ext_in,
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ext_out => ext_out,
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int_in => int_in,
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int_out => int_out
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);
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ext_in.control(1) <= clk;
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real_clk_proc: process
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begin
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for x in 0 to SIMULATION_CYCLE_COUNT*2 loop
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clk <= not clk;
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wait for CLK_PERIOD / 2;
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end loop;
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wait;
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end process real_clk_proc;
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verify_clk: process
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variable last_clk : std_logic;
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begin
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wait for CLK_PERIOD / 2;
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for x in 0 to SIMULATION_CYCLE_COUNT loop
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if last_clk = ext_out.control(1) then
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report "Secondary side clk not correct." severity error;
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end if;
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last_clk := ext_out.control(1);
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wait for CLK_PERIOD;
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end loop;
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wait;
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end process verify_clk;
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verify_out_signals: process
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variable curr_parity : std_logic;
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begin
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wait for CLK_PERIOD / 2;
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for x in 0 to SIMULATION_CYCLE_COUNT loop
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check_data_out(expected_out);
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check_parity(expected_out);
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wait for CLK_PERIOD;
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end loop;
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wait;
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end process verify_out_signals;
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verify_signals : process
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variable nsv: boolean;
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begin
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expected_out <= "00000000";
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wait for 3 * CLK_PERIOD;
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wait for CLK_PERIOD / 3;
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expected_out <= "00000000";
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check_next_state(IDLE);
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wait for CLK_PERIOD /4;
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check_next_state(TX_HEADER);
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wait for CLK_PERIOD * 3 / 4;
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expected_out <= get_cmd_bits(WRITE) & get_size_bits_sim(2);
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check_next_state(TX_BODY);
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wait for CLK_PERIOD;
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expected_out <= "00000001";
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check_next_state(TX_BODY);
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wait for CLK_PERIOD;
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expected_out <= "00000010";
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check_next_state(TX_ACK);
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wait for CLK_PERIOD;
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expected_out <= "00000000";
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check_next_state(TX_ACK);
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wait for CLK_PERIOD;
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check_next_state(IDLE);
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wait for CLK_PERIOD * 6;
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expected_out <= "00000000";
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check_next_state(IDLE);
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wait for CLK_PERIOD /4;
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check_next_state(TX_HEADER);
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wait for CLK_PERIOD * 3 / 4;
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expected_out <= get_cmd_bits(WRITE_ADD) & get_size_bits(2);
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check_next_state(ADDR1);
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wait for CLK_PERIOD;
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expected_out <= x"FA";
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check_next_state(ADDR2);
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wait for CLK_PERIOD;
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expected_out <= x"A0";
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check_next_state(ADDR3);
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wait for CLK_PERIOD;
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expected_out <= x"0F";
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check_next_state(ADDR4);
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wait for CLK_PERIOD;
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expected_out <= x"FA";
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check_next_state(TX_BODY);
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wait for CLK_PERIOD;
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expected_out <= "00000100";
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check_next_state(TX_BODY);
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wait for CLK_PERIOD;
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expected_out <= "00001000";
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check_next_state(TX_ACK);
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wait for CLK_PERIOD;
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expected_out <= "00000000";
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check_next_state(TX_ACK);
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wait for CLK_PERIOD;
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expected_out <= "00000000";
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check_next_state(IDLE);
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wait for CLK_PERIOD * 2;
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wait for CLK_PERIOD /4;
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check_next_state(RX_HEADER);
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wait for CLK_PERIOD * 3 / 4;
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expected_out <= get_cmd_bits(READ) & get_size_bits(2);
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check_next_state(RX_RESPONSE);
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wait for CLK_PERIOD;
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expected_out <= "00000000";
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check_next_state(RX_RESPONSE);
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wait for CLK_PERIOD;
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wait for CLK_PERIOD / 4;
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check_next_state(RX_BODY_NO_OUT);
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wait for CLK_PERIOD * 3 /4;
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check_next_state(RX_BODY);
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wait for CLK_PERIOD;
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check_next_state(RX_BODY);
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wait for CLK_PERIOD;
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check_next_state(IDLE);
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wait for CLK_PERIOD * 5;
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wait for CLK_PERIOD /4;
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check_next_state(RX_HEADER);
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wait for CLK_PERIOD * 3 / 4;
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expected_out <= get_cmd_bits(READ_ADD) & get_size_bits(2);
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check_next_state(ADDR1);
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wait for CLK_PERIOD;
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expected_out <= x"FA";
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check_next_state(ADDR2);
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wait for CLK_PERIOD;
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expected_out <= x"A0";
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check_next_state(ADDR3);
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wait for CLK_PERIOD;
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expected_out <= x"0F";
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check_next_state(ADDR4);
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wait for CLK_PERIOD;
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expected_out <= x"FA";
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check_next_state(RX_RESPONSE);
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wait for CLK_PERIOD;
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expected_out <= "00000000";
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check_next_state(RX_RESPONSE);
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wait for CLK_PERIOD;
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wait for CLK_PERIOD / 4;
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check_next_state(RX_BODY_NO_OUT);
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wait for CLK_PERIOD * 3 /4;
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check_next_state(RX_BODY);
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wait for CLK_PERIOD;
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check_next_state(RX_BODY);
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wait for CLK_PERIOD;
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check_next_state(IDLE);
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wait;
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end process verify_signals;
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command_stimulus: process
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begin
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cmd <= NO_OP;
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cmd_size <= 2;
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wait for 3*CLK_PERIOD;
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wait for CLK_PERIOD / 2;
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cmd <= WRITE;
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wait for CLK_PERIOD;
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cmd <= NO_OP;
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wait for CLK_PERIOD * 10;
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cmd <= WRITE_ADD;
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address <= x"FA0FA0FA";
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wait for CLK_PERIOD;
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cmd <= NO_OP;
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address <= (others => '0');
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wait for CLK_PERIOD * 10;
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cmd <= READ;
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wait for CLK_PERIOD;
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cmd <= NO_OP;
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wait for CLK_PERIOD * 10;
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cmd <= READ_ADD;
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address <= x"FA0FA0FA";
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wait for CLK_PERIOD;
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cmd <= NO_OP;
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address <= (others => '0');
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wait;
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end process command_stimulus;
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external_stimulus_signal: process(curr_word)
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begin
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ext_in.payload <= curr_word;
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ext_in.control(0) <= calc_parity(curr_word);
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end process external_stimulus_signal;
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external_stimulus: process
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begin
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rst <= '0';
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wait for CLK_PERIOD / 1000;
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rst <= '1';
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curr_word <= "00000000";
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wait for 999 * CLK_PERIOD / 1000;
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wait for 2 * CLK_PERIOD;
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rst <= '0';
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wait for CLK_PERIOD / 2;
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wait for 4* CLK_PERIOD;
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curr_word <= "00001001";
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wait for CLK_PERIOD;
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curr_word <= "00000000";
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wait for CLK_PERIOD * 14;
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curr_word <= "00101001";
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wait for CLK_PERIOD;
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curr_word <= "00000000";
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wait for CLK_PERIOD*5;
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curr_word <= "01000001";
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wait for CLK_PERIOD;
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curr_word <= "10000000";
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wait for CLK_PERIOD;
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curr_word <= "01000000";
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wait for CLK_PERIOD;
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curr_word <= "00000000";
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wait for CLK_PERIOD*12;
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curr_word <= "01100001";
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wait for CLK_PERIOD;
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curr_word <= "00100000";
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wait for CLK_PERIOD;
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curr_word <= "00010000";
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wait for CLK_PERIOD;
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curr_word <= "00000000";
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wait;
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end process external_stimulus;
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internal_stimulus: process
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begin
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int_out.is_full_in <= '0';
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int_out.write_enable_out <= '0';
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wait for 3 * CLK_PERIOD;
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-- stimulus goes here
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int_out.write_enable_out <= '1';
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int_out.payload <= "00000001";
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wait until rising_edge(clk) and int_in.is_full_out = '0';
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wait until falling_edge(clk);
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int_out.payload <= "00000010";
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wait until rising_edge(clk) and int_in.is_full_out = '0';
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wait until falling_edge(clk);
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int_out.payload <= "00000100";
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wait until rising_edge(clk) and int_in.is_full_out = '0';
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wait until falling_edge(clk);
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int_out.payload <= "00001000";
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wait until rising_edge(clk) and int_in.is_full_out = '0';
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wait until falling_edge(clk);
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int_out.payload <= "00010000";
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wait until int_in.is_full_out = '0';
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wait for CLK_PERIOD/2;
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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int_out.payload <= "00100000";
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wait until int_in.is_full_out = '0';
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wait for CLK_PERIOD/2;
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wait until rising_edge(clk);
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wait until rising_edge(clk); --- ??? Why all these rising_edge checks?
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wait;
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end process internal_stimulus;
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end architecture tb ;
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