remodeled entire project to use VHDL libraries

.gitignore

@@ -1,2 +1,2 @@
-*/wave
-*/work
+**/wave
+**/work

src/controller/control_unit.vhd

@@ -1,8 +1,8 @@
 library IEEE;  
 use IEEE.std_logic_1164.all;
 use IEEE.MATH_REAL.all;
-library work;
-use work.io_types.all;
+library ganimede;
+use ganimede.io_types.all;
 
 entity control_unit is
   
@@ -11,7 +11,7 @@ entity control_unit is
     ext_control_in  : in  ext_control_unit_in_t;
     ext_control_out : out ext_control_unit_out_t;
     int_control_in  : in  int_control_unit_in_t;
-    int_control_out : out int_control_unit_out_t;
+    int_control_out : out int_control_unit_out_t
   );
 
 end entity control_unit;
@@ -31,7 +31,7 @@ architecture behave of control_unit is
 
 begin
 
-  comb_proc: process(control_in, state)
+  comb_proc: process(ext_control_in, int_control_in, state)
   begin
     ored := '0';
     ready_reduction: for i in 0 to number_of_drivers - 1 loop
@@ -40,7 +40,7 @@ begin
     int_control_out.driver_id <= state.curr_driver;
     int_control_out.address <= state.address;
     int_control_out.seq_mem_access_count <= state.seq_mem_access_count;        
-    int_control_out.ready <= state.ready;
+    ext_control_out.ready <= state.ready;
     int_control_out.instruction <= state.instruction;
   end process comb_proc;
 

src/controller/control_unit_tb.vhd

@@ -1,9 +1,10 @@
 library IEEE;  
 use IEEE.std_logic_1164.all;
 use IEEE.MATH_REAL.all;
-use ieee.numeric_std.all;
-library work;
-use work.io_types.all;
+use IEEE.numeric_std.all;
+library ganimede;
+use ganimede.io_types.all;
+library controller;
 
 entity control_unit_tb is
 end entity control_unit_tb;
@@ -13,18 +14,14 @@ architecture tb of control_unit_tb is
   constant cycle: Time := 10 ns;
   signal clock: std_logic := '0';
   signal reset: std_logic := '0';
-  signal control_input: control_unit_in_t := (
-                                              (others => '0'),
+  signal ext_control_input: ext_control_unit_in_t := (
                                               (others => '0'),
                                               (others => '0'),
                                               (others => '0'),
                                               x"00");
-  signal control_output: control_unit_out_t := (
-                                              (others => '0'),
-                                              (others => '0'),
-                                              (others => '1'),
-                                              '1',
-                                              x"00");
+  signal int_control_input: int_control_unit_in_t := (active_driver => (others => '0'));
+  signal ext_control_output: ext_control_unit_out_t;
+  signal int_control_output: int_control_unit_out_t;
   signal current_driver : std_logic_vector(2 downto 0) := "000";
   shared variable word_counter: natural := 0;
 
@@ -39,23 +36,25 @@ begin
   wait;
   end process clock_proc;
 
-  control_unit_inst: entity work.control_unit
+  control_unit_inst: entity controller.control_unit
     port map(
-      clk => clock,
-      rst => reset,
-      control_in => control_input,
-      control_out => control_output
+    clk             => clock,
+    rst             => reset,
+    ext_control_in  => ext_control_input,
+    ext_control_out => ext_control_output,
+    int_control_in  => int_control_input,
+    int_control_out => int_control_output
     );
 
 stimulus_proc: process
 begin
   wait for cycle;
 
-  control_input.driver_id <= "010";
-  control_input.active_driver <= "000";
-  control_input.address <= x"F0F0F0F0";
-  control_input.seq_mem_access_count <= "00000011";
-  control_input.instruction <= x"81";
+  ext_control_input.driver_id <= "010";
+  int_control_input.active_driver <= "000";
+  ext_control_input.address <= x"F0F0F0F0";
+  ext_control_input.seq_mem_access_count <= "00000011";
+  ext_control_input.instruction <= x"81";
   word_counter := 3;
   wait for cycle;
   current_driver <= "010";
@@ -66,7 +65,7 @@ begin
     report "words remaining are " & integer'image(i);
   end loop for_loop;
   
-  control_input.active_driver <= "000";
+  int_control_input.active_driver <= "000";
   report "Stim process done";
   wait;
 end process stimulus_proc; 
@@ -77,9 +76,9 @@ begin
   wait for cycle;
 
   wait for cycle;
-  assert control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity error;
-  assert control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error;
-  assert control_output.instruction = x"81" report "Incorrect memory op from control_unit" severity error;
+  assert int_control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity error;
+  assert int_control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error;
+  assert int_control_output.instruction = x"81" report "Incorrect memory op from control_unit" severity error;
 
   wait for 5 * cycle;
   reset <= '1';

src/ganimede/control_socbridge_tb.vhd

@@ -3,7 +3,8 @@ use IEEE.std_logic_1164.all;
 use IEEE.NUMERIC_STD.all;
 library work;
 use work.io_types.all;
-use work.socbridge_driver_tb_pkg.all;
+library socbridge;
+use socbridge.tb_pkg.all;
 
 entity control_socbridge_tb is
 end entity control_socbridge_tb;

src/ganimede/io_type_pkg.vhd

@@ -21,12 +21,12 @@ package io_types is
     socbridge: ext_protocol_def_t;
   end record interface_inst_t;
 
-    type ext_control_unit_in_t is record
+  type ext_control_unit_in_t is record
     driver_id: std_logic_vector(number_of_drivers - 1 downto 0);
     address: std_logic_vector(address_width - 1 downto 0);
     seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
     instruction: std_logic_vector(inst_word_width - 1 downto 0);
-  end record control_unit_in_t;
+  end record ext_control_unit_in_t;
 
   type ext_control_unit_out_t is record
     ready: std_logic;
@@ -37,11 +37,11 @@ package io_types is
     address: std_logic_vector(address_width - 1 downto 0);
     seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
     instruction: std_logic_vector(inst_word_width - 1 downto 0);
-  end record control_unit_out_t;
+  end record int_control_unit_out_t;
 
   type int_control_unit_in_t is record
-    active_driver: std_logic_vector(number_of_drivers - 1 downto 0)
-  end record int_control_unit_out_t;
+    active_driver: std_logic_vector(number_of_drivers - 1 downto 0);
+  end record int_control_unit_in_t;
 
   --- PROTOCOL INFORMATION ---
   constant interface_inst : interface_inst_t := (

src/socbridge/socbridge_driver.vhd

@@ -2,8 +2,9 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.NUMERIC_STD.all;
 library work;
-use work.io_types.all;
 use work.socbridge_driver_tb_pkg.all;
+library ganimede;
+use ganimede.io_types.all;
 
 
 entity socbridge_driver is

src/socbridge/socbridge_driver_tb.vhd

@@ -2,8 +2,9 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.MATH_REAL.all;
 library work;
-use work.io_types.all;
 use work.socbridge_driver_tb_pkg.all;
+library ganimede;
+use ganimede.io_types.all;
 
 
 entity socbridge_driver_tb is

src/socbridge/socbridge_driver_tb_pkg.vhd

@@ -2,8 +2,8 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use IEEE.MATH_REAL.all;
-library work;
-use work.io_types.all;
+library ganimede;
+use ganimede.io_types.all;
 
 
 package socbridge_driver_tb_pkg is

src/test.vhd

@@ -1,27 +0,0 @@
-library IEEE;
-library work;
-use work.io_types.all;
-
-entity test is
-  port (
-    ext_interface_in    : in ext_interface_in_t;
-    ext_interface_out   : out ext_interface_out_t
-  );
-end entity test;
-
-architecture rtl of test is
-  signal int_interface_in  : int_interface_in_t;
-  signal int_interface_out : int_interface_out_t;
-begin
-  
-  proc_name: process
-  begin
-    
-  report "Hello";
-  report integer'image(ext_interface_in.socbridge.payload'length);
-  report integer'image(ext_interface_in.spi.payload'length);
-  wait;
-  end process proc_name;
-  
-  
-end architecture rtl;