46 lines
1.7 KiB
VHDL
46 lines
1.7 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.MATH_REAL.all;
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library ganimede;
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use ganimede.io_types.all;
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package management_types is
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constant WORD_SIZE : natural := 32;
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-- Amount to right shift addres to convert e.g 0x00000004 to 0x00000001 for 32-bit words
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constant address_shift : natural := natural(FLOOR(LOG2(real(WORD_SIZE) / real(8))));
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subtype manager_word_t is std_logic_vector(WORD_SIZE - 1 downto 0);
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constant empty_word : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0');
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constant mem_words : natural := 64;
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type memory_t is array (0 to mem_words - 1) of manager_word_t;
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-- Index in memory array where memory read address is kept.
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-- Read is active while it is not all zero.
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constant read_address_index : std_logic_vector(WORD_SIZE - 1 downto 0) := x"00000000";
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-- Index in memory array where memory write address is kept.
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-- Write is active while it is not all zero. Mutex with read address
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constant write_address_index : std_logic_vector(WORD_SIZE - 1 downto 0) := x"00000001";
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constant access_size : std_logic_vector(WORD_SIZE - 1 downto 0) := x"00000002";
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-- Status register for debugging
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type manager_state_t is record
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memory : memory_t;
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data_out : manager_word_t;
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end record manager_state_t;
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-- reset value of status register
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constant manager_state_reset_val : manager_state_t := ((others => (others => '0')), x"00000000");
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type socbridge_driver_to_manager_t is record
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address : manager_word_t;
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data : manager_word_t;
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valid: std_logic;
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end record socbridge_driver_to_manager_t;
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type manager_to_socbridge_driver_t is record
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data : manager_word_t;
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valid : std_logic;
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ready : std_logic;
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end record manager_to_socbridge_driver_t;
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end package;
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