26 lines
393 B
VHDL
26 lines
393 B
VHDL
library IEEE;
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library work;
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use work.io_types.all;
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entity test is
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port (
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t : in interface_arr_t(0 to interface_arr'length - 1)
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);
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end entity test;
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architecture rtl of test is
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begin
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proc_name: process
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begin
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for x in 0 to (interface_arr'length - 1) loop
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report interface_arr(x).name ;
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end loop;
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wait;
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end process proc_name;
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end architecture rtl;
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