85 lines
2.3 KiB
VHDL
85 lines
2.3 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.MATH_REAL.all;
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use ieee.numeric_std.all;
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library work;
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use work.io_types.all;
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entity control_unit_tb is
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end entity control_unit_tb;
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architecture tb of control_unit_tb is
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constant cycle: Time := 10 ns;
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signal clock: std_logic := '0';
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signal reset: std_logic := '0';
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signal control_input: control_unit_in_t := (
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(others => '0'),
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(others => '0'),
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(others => '0'),
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"00000011");
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signal control_output: control_unit_out_t := (
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(others => '0'),
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(others => '0'),
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(others => '1'),
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'1');
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signal current_driver : std_logic_vector(2 downto 0) := "000";
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shared variable word_counter: natural := 0;
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begin
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clock_proc: process
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begin
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for i in 0 to 50 loop
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wait for cycle / 2;
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clock <= not clock;
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end loop;
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wait;
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end process clock_proc;
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control_unit_inst: entity work.control_unit
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port map(
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clk => clock,
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rst => reset,
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control_in => control_input,
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control_out => control_output
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);
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stimulus_proc: process
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begin
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wait for cycle;
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control_input.driver_id <= "010";
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control_input.active_driver <= "000";
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control_input.address <= x"F0F0F0F0";
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control_input.seq_mem_access_count <= "00000111";
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word_counter := 3;
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wait for cycle;
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current_driver <= "010";
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report "entering loop with word_counter" & integer'image(word_counter);
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for_loop: for i in word_counter - 1 downto 0 loop
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wait for cycle;
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report "word counter is " & integer'image(word_counter);
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end loop for_loop;
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control_input.active_driver <= "000";
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report "Stim process done";
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wait;
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end process stimulus_proc;
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monitor_proc: process
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begin
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wait for cycle;
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wait for cycle;
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assert control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity error;
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assert control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error;
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wait for 5 * cycle;
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report "Monitor process done";
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wait;
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end process monitor_proc;
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end architecture tb;
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