111 lines
3.7 KiB
VHDL
111 lines
3.7 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.NUMERIC_STD.all;
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library gan_ganimede;
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use gan_ganimede.io_types.all;
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library gan_socbridge;
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use gan_socbridge.socbridge_driver_pkg.all;
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library gan_controller;
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entity ganimede_tb is
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end entity ganimede_tb;
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architecture tb of ganimede_tb is
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signal done : boolean := false;
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constant CLK_PERIOD : Time := 10 ns;
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constant SIMULATION_CYCLE_COUNT : integer := 2000;
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signal clk, rst : std_logic := '0';
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signal controller_to_socbridge_driver_cmd : instruction_command_t;
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signal controller_to_socbridge_driver_address : std_logic_vector(31 downto 0);
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signal cmd_size : positive;
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signal ext_to_ganimede : ext_to_ganimede_t := (socbridge => (
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payload => (others => '0'),
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control => (others => '0')
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));
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signal ganimede_to_ext : ganimede_to_ext_t;
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signal ganimede_to_ip : ganimede_to_ip_t;
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signal ganimede_to_manager : controller_to_manager_t;
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signal manager_to_ganimede : manager_to_controller_t := (
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driver_id => (others => '0'),
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address => (others => '0'),
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seq_mem_access_count => 0,
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cmd => (others => '0')
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);
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signal ip_to_ganimede : ip_to_ganimede_t := (socbridge => (
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payload => (others => '0'),
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write_enable_out => '0',
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is_full_in => '0'
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));
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signal manager_to_controller: manager_to_controller_t := (
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driver_id => (others => '0'),
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address => (others => '0'),
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seq_mem_access_count => 0,
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cmd => "00"
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);
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signal drivers_to_controller: drivers_to_controller_t := (socbridge => (is_active => '0'));
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signal controller_to_manager: controller_to_manager_t;
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signal controller_to_drivers: controller_to_drivers_t;
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begin
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ganimede_inst: entity gan_ganimede.ganimede_toplevel
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port map(
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clk => clk,
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rst => rst,
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manager_to_ganimede => manager_to_ganimede,
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ganimede_to_manager => ganimede_to_manager,
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ext_to_ganimede => ext_to_ganimede,
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ganimede_to_ext => ganimede_to_ext,
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ip_to_ganimede => ip_to_ganimede,
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ganimede_to_ip => ganimede_to_ip
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);
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ext_to_ganimede.socbridge.control(1) <= clk;
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real_clk_proc: process
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variable cycle_count :integer := 0;
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begin
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while (not done) and (cycle_count < MAX_CYCLE_COUNT) loop
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clk <= not clk;
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wait for CLK_PERIOD / 2;
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end loop;
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wait;
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end process real_clk_proc;
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stimulus_proc: process
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begin
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report "Starting Simulation Stimulus!";
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done <= false;
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rst <= '1';
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wait for 3 * CLK_PERIOD;
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report "Reset grace period ended, starting stimulus...";
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rst <= '0';
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report "Test finished, ending simultaion...";
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done <= true;
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wait;
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end process stimulus_proc;
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internal_stimulus: process
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variable input : positive := 1;
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begin
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ip_to_ganimede.socbridge.is_full_in <= '0';
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ip_to_ganimede.socbridge.write_enable_out <= '0';
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wait for 3 * CLK_PERIOD;
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-- stimulus goes here
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ip_to_ganimede.socbridge.write_enable_out <= '1';
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ip_to_ganimede.socbridge.payload <= std_logic_vector(to_unsigned(input, ip_to_ganimede.socbridge.payload'length));
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input := input + 1 mod 256;
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wait until rising_edge(clk) and ganimede_to_ip.socbridge.is_full_out = '0';
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wait until falling_edge(clk);
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for x in 0 to 1000 loop
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ip_to_ganimede.socbridge.payload <= std_logic_vector(to_unsigned(input, ip_to_ganimede.socbridge.payload'length));
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input := input + 1 mod 256;
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wait until rising_edge(clk) and ganimede_to_ip.socbridge.is_full_out = '0';
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wait until falling_edge(clk);
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end loop;
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wait;
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end process internal_stimulus;
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end architecture tb;
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