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testbench works

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Adam 2025-03-03 16:59:06 +01:00 committed by Erik Örtenberg
parent 968acd4e3a
commit 4c4d62554f
1 changed files with 11 additions and 2 deletions
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11
src/control_unit_tb.vhd
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@ -28,7 +28,14 @@ architecture tb of control_unit_tb is
begin
clock <= not clock after cycle / 2;
clock_proc: process
begin
for i in 0 to 50 loop
wait for cycle / 2;
clock <= not clock;
end loop;
wait;
end process clock_proc;
control_unit_inst: entity work.control_unit
port map(
@ -47,6 +54,8 @@ begin
control_input.address <= x"F0F0F0F0";
control_input.seq_mem_access_count <= "00000111";
word_counter := 3;
wait for cycle;
current_driver <= "010";
report "entering loop with word_counter" & integer'image(word_counter);
for_loop: for i in word_counter - 1 downto 0 loop