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5824ea5d9a
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added all required functionality for correct execution (except for read buffer aware reads)
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2025-05-28 17:02:46 +02:00 |
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a2917a3b04
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Dummy ip works
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2025-04-22 14:36:27 +02:00 |
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77de1ca975
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WIP: bi-dir socbridge driver (fiddling with tb memory atm)
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2025-04-21 15:20:44 +02:00 |
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f2a03fab24
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buffers appear to be working
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2025-04-18 20:02:39 +02:00 |
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6a6ebdef95
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Standardized fifo type adn full test debugging
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2025-04-18 15:27:34 +02:00 |
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48dff427d4
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Standardized fifo types and names
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2025-04-16 16:50:34 +02:00 |
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554e3cadab
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buffer probably done but untested, need to rework ganimede toplevel
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2025-04-15 18:06:34 +02:00 |
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fccf2dbba3
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PRIMITIVE SUCCESS: made ganimede work in simulation (only 4 byte r/w to ganimede)
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2025-04-09 15:24:55 +02:00 |
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b56ce3a590
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Added prefix "gan_" to all libraries
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2025-04-08 16:20:19 +02:00 |
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11b42f3211
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Renamed some types
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2025-04-08 14:52:43 +02:00 |
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2b85765e1f
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made ganimede synthesizable
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2025-04-07 12:21:20 +02:00 |
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ffa2ee768c
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added grlib support (socbridge needs to be recompiled)
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2025-04-03 16:14:26 +02:00 |
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88dcd19a47
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Refactored controller types to support multiple drivers. Also started ganimede tb
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2025-03-14 17:01:15 +01:00 |
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10d519301e
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Started working on implementing units in top level
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2025-03-13 17:20:28 +01:00 |
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c3d3cef7c9
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Refactoring done
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2025-03-13 16:28:39 +01:00 |
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cd2c920c48
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remodeled entire project to use VHDL libraries
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2025-03-06 14:25:22 +01:00 |
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