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97256e8f47
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0dd3098c72
| Author | SHA1 | Date | |
|---|---|---|---|
| 0dd3098c72 | |||
| ac2aa8df19 |
@ -53,20 +53,22 @@ begin
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manager_to_socbridge_driver.ready <= '1';
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manager_to_socbridge_driver.ready <= '1';
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manager_to_socbridge_driver.data <= pack(manager_state.memory(local_word_address));
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manager_to_socbridge_driver.data <= pack(manager_state.memory(local_word_address));
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manager_to_socbridge_driver.valid <= '1';
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manager_to_socbridge_driver.valid <= '1';
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word_address <= local_word_address;
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word_address <= local_word_address;
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manager_to_controller.cmd <= cmd;
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manager_to_controller.cmd <= cmd;
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end process comb_proc;
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end process comb_proc;
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-- tre sorters sätt att avsluta en skrivning:
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-- tre sorters sätt att avsluta en skrivning:
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-- timeout om vi villha det
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-- timeout om vi villha det
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-- en lastbit genooom axi interface
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-- en lastbit genom axi interface
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-- vi har fått all data vi begärde.
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-- vi har fått all data vi begärde.
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seq_proc: process(clk)
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seq_proc: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if rst = '1' then
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if rst = '1' then
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manager_state <= manager_state_reset_val;
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manager_state.data_out <= manager_word_reset_val;
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manager_state.memory(0).reserved(0) <= '0';
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manager_state.memory(1).reserved(0) <= '0';
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else
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else
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-- Write data from SoCBridge driver to address
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-- Write data from SoCBridge driver to address
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if socbridge_driver_to_manager.valid = '1' then
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if socbridge_driver_to_manager.valid = '1' then
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@ -78,20 +80,20 @@ begin
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-- Is the controller done executing an instruction
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-- Is the controller done executing an instruction
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else
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else
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if controller_to_manager.done_reading = '1' then
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if controller_to_manager.done_reading = '1' then
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manager_state.memory(0) <= manager_word_reset_val;
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manager_state.memory(0).reserved(0) <= '0';
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end if;
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end if;
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if controller_to_manager.done_writing = '1' then
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if controller_to_manager.done_writing = '1' then
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manager_state.memory(1) <= manager_word_reset_val;
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manager_state.memory(1).reserved(0) <= '0';
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end if;
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end if;
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end if;
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end if;
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-- Is there a read instruction in memory
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-- Is there a read instruction in memory
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if pack(read_address) /= empty_word and controller_to_manager.ready = '1' and controller_to_manager.done_reading = '0' then
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if read_address.reserved(0) = '1' and controller_to_manager.ready = '1' and controller_to_manager.done_reading = '0' then
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manager_to_controller.address <= read_address.address & "0000000000";
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manager_to_controller.address <= read_address.address & "0000000000";
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manager_to_controller.driver_id <= "1"; -- Only supprts one driver at present
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manager_to_controller.driver_id <= "1"; -- Only supprts one driver at present
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manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10;
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manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10;
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cmd <= "10";
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cmd <= "10";
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-- Is there a write instruction in memory
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-- Is there a write instruction in memory
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elsif pack(write_address) /= empty_word and controller_to_manager.ready = '1' and controller_to_manager.done_writing = '0'then
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elsif write_address.reserved(0) = '1' and controller_to_manager.ready = '1' and controller_to_manager.done_writing = '0'then
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manager_to_controller.address <= write_address.address & "0000000000";
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manager_to_controller.address <= write_address.address & "0000000000";
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manager_to_controller.driver_id <= "1"; -- Only supports one driver at present
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manager_to_controller.driver_id <= "1"; -- Only supports one driver at present
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manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10;
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manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10;
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@ -16,7 +16,8 @@ package management_types is
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reserved: std_logic_vector(WORD_SIZE - 1 - (22 + 4 + 3) downto 0);
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reserved: std_logic_vector(WORD_SIZE - 1 - (22 + 4 + 3) downto 0);
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end record manager_word_t;
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end record manager_word_t;
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constant empty_word : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0');
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constant empty_word : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0');
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constant mem_words : natural := 64;
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constant mem_words : natural := 2;
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constant min_bits_to_determine_address : natural := natural(CEIL(LOG2(real(mem_words))));
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constant address_mask : std_logic_vector(WORD_SIZE - 1 downto 0) := std_logic_vector(to_unsigned(mem_words - 1, 32));
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constant address_mask : std_logic_vector(WORD_SIZE - 1 downto 0) := std_logic_vector(to_unsigned(mem_words - 1, 32));
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type memory_t is array (0 to mem_words - 1) of manager_word_t;
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type memory_t is array (0 to mem_words - 1) of manager_word_t;
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