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2 changed files with 11 additions and 8 deletions

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@ -53,20 +53,22 @@ begin
manager_to_socbridge_driver.ready <= '1'; manager_to_socbridge_driver.ready <= '1';
manager_to_socbridge_driver.data <= pack(manager_state.memory(local_word_address)); manager_to_socbridge_driver.data <= pack(manager_state.memory(local_word_address));
manager_to_socbridge_driver.valid <= '1'; manager_to_socbridge_driver.valid <= '1';
word_address <= local_word_address; word_address <= local_word_address;
manager_to_controller.cmd <= cmd; manager_to_controller.cmd <= cmd;
end process comb_proc; end process comb_proc;
-- tre sorters sätt att avsluta en skrivning: -- tre sorters sätt att avsluta en skrivning:
-- timeout om vi villha det -- timeout om vi villha det
-- en lastbit genooom axi interface -- en lastbit genom axi interface
-- vi har fått all data vi begärde. -- vi har fått all data vi begärde.
seq_proc: process(clk) seq_proc: process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
manager_state <= manager_state_reset_val; manager_state.data_out <= manager_word_reset_val;
manager_state.memory(0).reserved(0) <= '0';
manager_state.memory(1).reserved(0) <= '0';
else else
-- Write data from SoCBridge driver to address -- Write data from SoCBridge driver to address
if socbridge_driver_to_manager.valid = '1' then if socbridge_driver_to_manager.valid = '1' then
@ -78,20 +80,20 @@ begin
-- Is the controller done executing an instruction -- Is the controller done executing an instruction
else else
if controller_to_manager.done_reading = '1' then if controller_to_manager.done_reading = '1' then
manager_state.memory(0) <= manager_word_reset_val; manager_state.memory(0).reserved(0) <= '0';
end if; end if;
if controller_to_manager.done_writing = '1' then if controller_to_manager.done_writing = '1' then
manager_state.memory(1) <= manager_word_reset_val; manager_state.memory(1).reserved(0) <= '0';
end if; end if;
end if; end if;
-- Is there a read instruction in memory -- Is there a read instruction in memory
if pack(read_address) /= empty_word and controller_to_manager.ready = '1' and controller_to_manager.done_reading = '0' then if read_address.reserved(0) = '1' and controller_to_manager.ready = '1' and controller_to_manager.done_reading = '0' then
manager_to_controller.address <= read_address.address & "0000000000"; manager_to_controller.address <= read_address.address & "0000000000";
manager_to_controller.driver_id <= "1"; -- Only supprts one driver at present manager_to_controller.driver_id <= "1"; -- Only supprts one driver at present
manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10; manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10;
cmd <= "10"; cmd <= "10";
-- Is there a write instruction in memory -- Is there a write instruction in memory
elsif pack(write_address) /= empty_word and controller_to_manager.ready = '1' and controller_to_manager.done_writing = '0'then elsif write_address.reserved(0) = '1' and controller_to_manager.ready = '1' and controller_to_manager.done_writing = '0'then
manager_to_controller.address <= write_address.address & "0000000000"; manager_to_controller.address <= write_address.address & "0000000000";
manager_to_controller.driver_id <= "1"; -- Only supports one driver at present manager_to_controller.driver_id <= "1"; -- Only supports one driver at present
manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10; manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10;

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@ -16,7 +16,8 @@ package management_types is
reserved: std_logic_vector(WORD_SIZE - 1 - (22 + 4 + 3) downto 0); reserved: std_logic_vector(WORD_SIZE - 1 - (22 + 4 + 3) downto 0);
end record manager_word_t; end record manager_word_t;
constant empty_word : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0'); constant empty_word : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0');
constant mem_words : natural := 64; constant mem_words : natural := 2;
constant min_bits_to_determine_address : natural := natural(CEIL(LOG2(real(mem_words))));
constant address_mask : std_logic_vector(WORD_SIZE - 1 downto 0) := std_logic_vector(to_unsigned(mem_words - 1, 32)); constant address_mask : std_logic_vector(WORD_SIZE - 1 downto 0) := std_logic_vector(to_unsigned(mem_words - 1, 32));
type memory_t is array (0 to mem_words - 1) of manager_word_t; type memory_t is array (0 to mem_words - 1) of manager_word_t;