117 lines
4.2 KiB
VHDL
117 lines
4.2 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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library gan_ganimede;
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use gan_ganimede.io_types.all;
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library gan_socbridge;
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use gan_socbridge.socbridge_driver_pkg.all;
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library gan_controller;
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library gan_manager;
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use gan_manager.management_types.all;
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library gan_buffer;
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entity ganimede_toplevel is
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port (
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clk : in std_logic;
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rst : in std_logic;
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ext_to_ganimede : in ext_to_ganimede_t;
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ganimede_to_ext : out ganimede_to_ext_t;
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ip_to_ganimede : in ip_to_ganimede_t;
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ganimede_to_ip : out ganimede_to_ip_t
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);
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end entity ganimede_toplevel;
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architecture rtl of ganimede_toplevel is
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--- SIGNAL DECLERATIONS ---
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signal drivers_to_controller : drivers_to_controller_t;
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signal controller_to_drivers : controller_to_drivers_t;
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signal manager_to_controller : manager_to_controller_t;
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signal controller_to_manager : controller_to_manager_t;
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signal socbridge_driver_to_manager : socbridge_driver_to_manager_t;
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signal manager_to_socbridge_driver : manager_to_socbridge_driver_t;
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signal socbridge_driver_to_buffer : fifo_interface_t;
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signal buffer_to_socbridge_driver : fifo_interface_t;
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signal socbridge_clk : std_logic;
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signal used_slots : integer;
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--signal gan_socbridge_WE_in : std_logic;
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--signal gan_socbridge_WE_out : std_logic;
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--signal gan_socbridge_is_full_in : std_logic;
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--signal gan_socbridge_is_full_out : std_logic;
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begin
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--- CONNECT EXTERNAL SIGNALS TO INTERNAL CONNECTIONS ---
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--- DRIVER INSTANTIATION ---
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socbridge_driver_inst: entity gan_socbridge.socbridge_driver
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port map(
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clk => clk,
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socbridge_clk => socbridge_clk,
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rst => rst,
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controller_to_socbridge_driver => controller_to_drivers.socbridge,
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socbridge_driver_to_controller => drivers_to_controller.socbridge,
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manager_to_socbridge_driver => manager_to_socbridge_driver,
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socbridge_driver_to_manager => socbridge_driver_to_manager,
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ext_to_socbridge_driver => ext_to_ganimede.socbridge,
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socbridge_driver_to_ext => ganimede_to_ext.socbridge,
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ip_to_socbridge_driver => buffer_to_socbridge_driver,
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socbridge_driver_to_ip => socbridge_driver_to_buffer,
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used_slots => used_slots
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);
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controller_inst: entity gan_controller.control_unit
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port map(
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clk => clk,
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rst => rst,
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manager_to_controller => manager_to_controller,
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controller_to_manager => controller_to_manager,
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drivers_to_controller => drivers_to_controller,
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controller_to_drivers => controller_to_drivers
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);
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manager_inst: entity gan_manager.management_unit
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port map(
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clk => clk,
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rst => rst,
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manager_to_controller => manager_to_controller,
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controller_to_manager => controller_to_manager,
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manager_to_socbridge_driver => manager_to_socbridge_driver,
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socbridge_driver_to_manager => socbridge_driver_to_manager
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);
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fifo_buffer_to_ip_inst : entity gan_buffer.fifo_buffer
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generic map (
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buffer_size => 2*1024
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)
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port map(
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in_clk => socbridge_clk,
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out_clk => clk,
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rst => rst,
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ready_in => ip_to_ganimede.socbridge.ready,
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ready_out => buffer_to_socbridge_driver.ready,
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valid_in => socbridge_driver_to_buffer.valid,
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valid_out => ganimede_to_ip.socbridge.valid,
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data_in => socbridge_driver_to_buffer.data,
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data_out => ganimede_to_ip.socbridge.data
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);
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fifo_buffer_from_ip_inst : entity gan_buffer.fifo_buffer
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generic map (
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buffer_size => 2*1024
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)
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port map(
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in_clk => clk,
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out_clk => socbridge_clk,
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rst => rst,
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ready_in => socbridge_driver_to_buffer.ready,
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ready_out => ganimede_to_ip.socbridge.ready,
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valid_in => ip_to_ganimede.socbridge.valid,
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valid_out => buffer_to_socbridge_driver.valid,
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data_in => ip_to_ganimede.socbridge.data,
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data_out => buffer_to_socbridge_driver.data,
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used_slots => used_slots
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);
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--- LATER WE ADD OPTIMIZATIONS HERE ---
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end architecture rtl;
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