Restored gtkwave file for socbridge driver testbench

.gitignore

@@ -1,2 +1,4 @@
 **/wave
 **/work
+**/syn
+scripts/ghdl

scripts/ghdl

@@ -1,4 +0,0 @@
-#!/bin/bash
-VARS="$@"
-COMMAND="ghdl $VARS"
-docker run -it -v .:/src -w /src ghdl/ghdl:5.0.0-dev-gcc-ubuntu-24.04 bash -c "$COMMAND" 

scripts/source_and_run.sh

@@ -1,6 +0,0 @@
-#!/bin/bash
-
-source /gsl/cad/modules/init/bash
-
-module add /gsl/cad/modules/modulefiles/nanoxplore/nxdesignsuite/24.3.0.0
-nxpython $@

src/.gitignore

@@ -0,0 +1 @@
+**/grlib*/**

src/control_socbridge_merge/control_socbridge_tb.vhd

@@ -3,8 +3,8 @@ use IEEE.std_logic_1164.all;
 use IEEE.NUMERIC_STD.all;
 library ganimede;
 use ganimede.io_types.all;
-library socbridge;
-use socbridge.socbridge_driver_tb_pkg.all;
+library gan_socbridge;
+use gan_socbridge.socbridge_driver_tb_pkg.all;
 library controller;
 
 entity control_socbridge_tb is
@@ -23,8 +23,8 @@ architecture tb of control_socbridge_tb is
     control => (others => '0')
   );
   signal socbridge_driver_to_ext    :  socbridge_driver_to_ext_t;
-  signal socbridge_driver_to_buffer :  socbridge_driver_to_buffer_t;
-  signal buffer_to_socbridge_driver :  buffer_to_socbridge_driver_t := (
+  signal socbridge_driver_to_ip :  socbridge_driver_to_ip_t;
+  signal ip_to_socbridge_driver :  ip_to_socbridge_driver_t := (
     payload => (others => '0'),
     write_enable_out => '0',
     is_full_in => '0'
@@ -35,9 +35,9 @@ architecture tb of control_socbridge_tb is
     seq_mem_access_count => 0,
     cmd => "00"
   );
-  signal socbridge_driver_to_controller: socbridge_driver_to_controller_t := (is_active => '0');
+  signal drivers_to_controller: drivers_to_controller_t := (socbridge => (is_active => '0'));
   signal controller_to_cpu: controller_to_cpu_t;
-  signal controller_to_socbridge_driver: controller_to_socbridge_driver_t;
+  signal controller_to_drivers: controller_to_drivers_t;
 
   signal curr_word : std_logic_vector(ext_to_socbridge_driver.payload'length - 1 downto 0);
   signal expected_out : std_logic_vector(socbridge_driver_to_ext.payload'length - 1 downto 0);
@@ -80,12 +80,12 @@ begin
     port map(
       clk                            => clk,
       rst                            => rst,
-      controller_to_socbridge_driver => controller_to_socbridge_driver,
-      socbridge_driver_to_controller => socbridge_driver_to_controller, 
+      controller_to_socbridge_driver => controller_to_drivers.socbridge,
+      socbridge_driver_to_controller => drivers_to_controller.socbridge, 
       ext_to_socbridge_driver        => ext_to_socbridge_driver,
       socbridge_driver_to_ext        => socbridge_driver_to_ext,
-      buffer_to_socbridge_driver     => buffer_to_socbridge_driver,
-      socbridge_driver_to_buffer     => socbridge_driver_to_buffer
+      ip_to_socbridge_driver         => ip_to_socbridge_driver,
+      socbridge_driver_to_ip         => socbridge_driver_to_ip
     );
 
   controller_unit_inst: entity controller.control_unit
@@ -94,8 +94,8 @@ begin
       rst                            => rst,
       cpu_to_controller              => cpu_to_controller,
       controller_to_cpu              => controller_to_cpu,
-      socbridge_driver_to_controller => socbridge_driver_to_controller,
-      controller_to_socbridge_driver => controller_to_socbridge_driver
+      drivers_to_controller          => drivers_to_controller,
+      controller_to_drivers          => controller_to_drivers
   );
   
   ext_to_socbridge_driver.control(1) <= clk;
@@ -121,21 +121,21 @@ begin
     rst <= '0';
     cpu_to_controller.address <= x"FA0FA0FA";
     cpu_to_controller.cmd <= "01";
-    wait until socbridge_driver_to_controller.is_active = '1';
+    wait until drivers_to_controller.socbridge.is_active = '1';
     report "Task received in driver, awaiting completion...";
     cpu_to_controller.address <= (others => '0');
     cpu_to_controller.cmd <= "00";
-    wait until socbridge_driver_to_controller.is_active = '0';
+    wait until drivers_to_controller.socbridge.is_active = '0';
     wait for CLK_PERIOD;
     report "Task completed in driver, sending next task...";
     cpu_to_controller.address <= x"FA0FA0FA";
     cpu_to_controller.cmd <= "10";
     wait for CLK_PERIOD;
-    wait until socbridge_driver_to_controller.is_active = '1';
+    wait until drivers_to_controller.socbridge.is_active = '1';
     report "Task received in driver, awaiting completion...";
     cpu_to_controller.address <= (others => '0');
     cpu_to_controller.cmd <= "00";
-    wait until socbridge_driver_to_controller.is_active = '0';
+    wait until drivers_to_controller.socbridge.is_active = '0';
     wait for CLK_PERIOD;
     report "Task completed in driver, ending simulation stimulus";
     cpu_to_controller.address <= (others => '0');
@@ -197,19 +197,19 @@ begin
   internal_stimulus: process
     variable input : positive := 1;
   begin
-    buffer_to_socbridge_driver.is_full_in <= '0';
-    buffer_to_socbridge_driver.write_enable_out <= '0';
+    ip_to_socbridge_driver.is_full_in <= '0';
+    ip_to_socbridge_driver.write_enable_out <= '0';
     wait for 3 * CLK_PERIOD;
     -- stimulus goes here
-    buffer_to_socbridge_driver.write_enable_out <= '1';
-    buffer_to_socbridge_driver.payload <= std_logic_vector(to_unsigned(input, buffer_to_socbridge_driver.payload'length));
+    ip_to_socbridge_driver.write_enable_out <= '1';
+    ip_to_socbridge_driver.payload <= std_logic_vector(to_unsigned(input, ip_to_socbridge_driver.payload'length));
     input := input + 1 mod 256;
-    wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0';
+    wait until rising_edge(clk) and socbridge_driver_to_ip.is_full_out = '0';
     wait until falling_edge(clk);
     for x in 0 to 1000 loop
-      buffer_to_socbridge_driver.payload <= std_logic_vector(to_unsigned(input, buffer_to_socbridge_driver.payload'length));
+      ip_to_socbridge_driver.payload <= std_logic_vector(to_unsigned(input, ip_to_socbridge_driver.payload'length));
       input := input + 1 mod 256;
-      wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0';
+      wait until rising_edge(clk) and socbridge_driver_to_ip.is_full_out = '0';
       wait until falling_edge(clk);
     end loop;
     wait;

src/controller/control_unit.vhd

@@ -7,11 +7,11 @@ use ganimede.io_types.all;
 entity control_unit is
   
   port (
-    clk, rst        : in  std_logic;
-    cpu_to_controller  : in  cpu_to_controller_t;
-    controller_to_cpu : out controller_to_cpu_t;
-    socbridge_driver_to_controller  : in  socbridge_driver_to_controller_t;
-    controller_to_socbridge_driver : out controller_to_socbridge_driver_t
+    clk, rst              : in  std_logic;
+    manager_to_controller     : in  manager_to_controller_t;
+    controller_to_manager     : out controller_to_manager_t;
+    drivers_to_controller : in  drivers_to_controller_t;
+    controller_to_drivers : out controller_to_drivers_t
   );
 
 end entity control_unit;
@@ -31,17 +31,17 @@ architecture behave of control_unit is
 
 begin
 
-  comb_proc: process(cpu_to_controller, socbridge_driver_to_controller, state)
+  comb_proc: process(manager_to_controller, drivers_to_controller, state)
   begin
     ored := '0';
     ready_reduction: for i in 0 to number_of_drivers - 1 loop
-      ored := ored or socbridge_driver_to_controller.is_active;
+      ored := ored or drivers_to_controller.socbridge.is_active;
     end loop ready_reduction;
-    controller_to_socbridge_driver.request <= state.curr_driver;
-    controller_to_socbridge_driver.address <= state.address;
-    controller_to_socbridge_driver.seq_mem_access_count <= state.seq_mem_access_count;        
-    controller_to_cpu.ready <= state.ready;
-    controller_to_socbridge_driver.instruction <= state.instruction;
+    controller_to_drivers.socbridge.request <= state.curr_driver;
+    controller_to_drivers.socbridge.address <= state.address;
+    controller_to_drivers.socbridge.seq_mem_access_count <= state.seq_mem_access_count;        
+    controller_to_manager.ready <= state.ready;
+    controller_to_drivers.socbridge.instruction <= state.instruction;
   end process comb_proc;
 
   sync_proc: process(clk, state)
@@ -56,10 +56,10 @@ begin
       else
         state.ready <= not ored;
         if ored = '0' then
-          state.address <= cpu_to_controller.address;
-          state.seq_mem_access_count <= cpu_to_controller.seq_mem_access_count;
-          state.curr_driver <= cpu_to_controller.driver_id(0);
-          with cpu_to_controller.cmd select
+          state.address <= manager_to_controller.address;
+          state.seq_mem_access_count <= manager_to_controller.seq_mem_access_count;
+          state.curr_driver <= manager_to_controller.driver_id(0);
+          with manager_to_controller.cmd select
             state.instruction <= WRITE when "01",
                                  READ  when "10",
                                  NO_OP when others;

src/controller/control_unit_tb.vhd

@@ -14,14 +14,14 @@ architecture tb of control_unit_tb is
   constant cycle: Time := 10 ns;
   signal clock: std_logic := '0';
   signal reset: std_logic := '0';
-  signal cpu_to_controller: cpu_to_controller_t := (
+  signal manager_to_controller: manager_to_controller_t := (
                                               (others => '0'),
                                               (others => '0'),
                                               0,
                                               "00");
-  signal socbridge_driver_to_controller: socbridge_driver_to_controller_t := (is_active => '0');
-  signal controller_to_cpu: controller_to_cpu_t;
-  signal controller_to_socbridge_driver: controller_to_socbridge_driver_t;
+  signal drivers_to_controller: drivers_to_controller_t := (socbridge => (is_active => '0'));
+  signal controller_to_manager: controller_to_manager_t;
+  signal controller_to_drivers: controller_to_drivers_t;
   signal current_driver : std_logic_vector(0 downto 0) := "0";
   shared variable word_counter: natural := 0;
 
@@ -40,21 +40,21 @@ begin
     port map(
     clk             => clock,
     rst             => reset,
-    cpu_to_controller  => cpu_to_controller,
-    controller_to_cpu => controller_to_cpu,
-    socbridge_driver_to_controller  => socbridge_driver_to_controller,
-    controller_to_socbridge_driver => controller_to_socbridge_driver
+    manager_to_controller  => manager_to_controller,
+    controller_to_manager => controller_to_manager,
+    drivers_to_controller => drivers_to_controller,
+    controller_to_drivers => controller_to_drivers
     );
 
 stimulus_proc: process
 begin
   wait for cycle;
 
-  cpu_to_controller.driver_id <= "1";
-  socbridge_driver_to_controller.is_active <= '0';
-  cpu_to_controller.address <= x"F0F0F0F0";
-  cpu_to_controller.seq_mem_access_count <= 3;
-  cpu_to_controller.cmd <= "01";
+  manager_to_controller.driver_id <= "1";
+  drivers_to_controller.socbridge.is_active <= '0';
+  manager_to_controller.address <= x"F0F0F0F0";
+  manager_to_controller.seq_mem_access_count <= 3;
+  manager_to_controller.cmd <= "01";
   word_counter := 3;
   wait for cycle;
   current_driver <= "1";
@@ -65,7 +65,7 @@ begin
     report "words remaining are " & integer'image(i);
   end loop for_loop;
   
-  socbridge_driver_to_controller.is_active <= '0';
+  drivers_to_controller.socbridge.is_active <= '0';
   report "Stim process done";
   wait;
 end process stimulus_proc; 
@@ -76,9 +76,9 @@ begin
   wait for cycle;
 
   wait for cycle;
-  assert controller_to_socbridge_driver.request = '1' report "Incorrect driver_id from control_unit" severity error;
-  assert controller_to_socbridge_driver.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error;
-  assert controller_to_socbridge_driver.instruction = WRITE report "Incorrect memory op from control_unit" severity error;
+  assert controller_to_drivers.socbridge.request = '1' report "Incorrect driver_id from control_unit" severity error;
+  assert controller_to_drivers.socbridge.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error;
+  assert controller_to_drivers.socbridge.instruction = WRITE report "Incorrect memory op from control_unit" severity error;
 
   wait for 5 * cycle;
   reset <= '1';

src/ganimede/ganimede.vhd

@@ -1,24 +1,32 @@
 library IEEE;
 use IEEE.std_logic_1164.all;
-library work;
-use work.io_types.all;
+library ganimede;
+use ganimede.io_types.all;
+library gan_socbridge;
+use gan_socbridge.socbridge_driver_tb_pkg.all;
+library controller;
 
-entity ganimede is
+entity ganimede_toplevel is
   port (
-    clk                 : in std_logic;
-    reset               : in std_logic;
-    ext_interface_in    : in ext_interface_in_t;
-    ext_interface_out   : out ext_interface_out_t;
-    int_interface_in    : in int_interface_in_t;
-    int_interface_out   : out int_interface_out_t
+    clk               : in  std_logic;
+    rst               : in  std_logic;
+    manager_to_ganimede   : in  manager_to_controller_t;
+    ganimede_to_manager   : out controller_to_manager_t;
+    ext_to_ganimede   : in  ext_to_ganimede_t;
+    ganimede_to_ext   : out ganimede_to_ext_t;
+    ip_to_ganimede    : in  ip_to_ganimede_t;
+    ganimede_to_ip    : out ganimede_to_ip_t
   );
-end entity ganimede;
-architecture rtl of ganimede is
+end entity ganimede_toplevel;
+architecture rtl of ganimede_toplevel is
   --- SIGNAL DECLERATIONS ---
-  signal gan_int_interface_in  : int_interface_in_t;
-  signal gan_int_interface_out : int_interface_out_t;
-  signal gan_ext_interface_in  : ext_interface_in_t;
-  signal gan_ext_interface_out : ext_interface_out_t;
+  signal ext_to_drivers        : ext_to_ganimede_t;
+  signal drivers_to_ext        : ganimede_to_ext_t;
+  signal drivers_to_ip         : ganimede_to_ip_t;
+  signal ip_to_drivers         : ip_to_ganimede_t;
+  signal drivers_to_controller : drivers_to_controller_t;
+  signal controller_to_drivers : controller_to_drivers_t;
+
 
   --signal gan_socbridge_WE_in : std_logic;
   --signal gan_socbridge_WE_out : std_logic;
@@ -38,34 +46,34 @@ architecture rtl of ganimede is
   --    data_out     : out std_logic_vector(WIDTH - 1 downto 0)
   --  );
   --end component;
-
-  component socbridge_driver is
-    port(
-      clk     : in std_logic;
-      reset   : in std_logic;
-      ext_in  : in ext_to_socbridge_driver_t;
-      ext_out : out socbridge_driver_to_ext_t;
-      int_in  : out buffer_to_socbridge_driver_t;
-      int_out : in socbridge_driver_to_buffer_t
-    );
-  end component;
-
 begin
   --- CONNECT EXTERNAL SIGNALS TO INTERNAL CONNECTIONS ---
-  gan_int_interface_in  <= int_interface_in;
-  int_interface_out     <= gan_int_interface_out;
-  gan_ext_interface_in  <= ext_interface_in;
-  ext_interface_out     <= gan_ext_interface_out;
-  
+  ip_to_drivers   <= ip_to_ganimede;
+  ganimede_to_ip  <= drivers_to_ip;
+  ext_to_drivers  <= ext_to_ganimede;
+  ganimede_to_ext <= drivers_to_ext;
+
   --- DRIVER INSTANTIATION ---
-  socbridge_driver_inst: socbridge_driver
-   port map(
-      clk     => clk,
-      reset   => reset,
-      ext_in  => gan_ext_interface_in.socbridge,
-      ext_out => gan_ext_interface_out.socbridge,
-      int_in  => gan_int_interface_in.socbridge,
-      int_out => gan_int_interface_out.socbridge
+  socbridge_inst: entity gan_socbridge.socbridge_driver
+    port map(
+      clk                            => clk,
+      rst                            => rst,
+      controller_to_socbridge_driver => controller_to_drivers.socbridge,
+      socbridge_driver_to_controller => drivers_to_controller.socbridge,
+      ext_to_socbridge_driver        => ext_to_ganimede.socbridge,
+      socbridge_driver_to_ext        => ganimede_to_ext.socbridge,
+      ip_to_socbridge_driver         => ip_to_ganimede.socbridge,
+      socbridge_driver_to_ip         => ganimede_to_ip.socbridge
+    );
+
+  controller_unit_inst: entity controller.control_unit
+    port map(
+      clk                            => clk,
+      rst                            => rst,
+      manager_to_controller              => manager_to_ganimede,
+      controller_to_manager              => ganimede_to_manager,
+      drivers_to_controller          => drivers_to_controller,
+      controller_to_drivers          => controller_to_drivers
   );
 
   --- LATER WE ADD OPTIMIZATIONS HERE ---

src/ganimede/ganimede_tb.vhd

@@ -0,0 +1,215 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+library ganimede;
+use ganimede.io_types.all;
+library gan_socbridge;
+use gan_socbridge.socbridge_driver_tb_pkg.all;
+library controller;
+
+entity ganimede_tb is
+end entity ganimede_tb;
+
+architecture tb of ganimede_tb is
+
+  constant CLK_PERIOD                           : Time := 10 ns;
+  constant SIMULATION_CYCLE_COUNT               : integer := 2000;
+  signal clk, rst                               : std_logic := '0';
+  signal controller_to_socbridge_driver_cmd     : command_t;
+  signal controller_to_socbridge_driver_address : std_logic_vector(31 downto 0);
+  signal cmd_size                               : positive;
+  signal ext_to_ganimede                : ext_to_ganimede_t := (socbridge => (
+    payload => (others => '0'),
+    control => (others => '0')
+  ));
+  signal ganimede_to_ext : ganimede_to_ext_t;
+  signal ganimede_to_ip  : ganimede_to_ip_t;
+  signal ganimede_to_cpu : controller_to_cpu_t;
+  signal cpu_to_ganimede : cpu_to_controller_t := (
+    driver_id => (others => '0'),
+    address => (others => '0'),
+    seq_mem_access_count => 0,
+    cmd => (others => '0')
+  );
+  signal ip_to_ganimede : ip_to_ganimede_t := (socbridge => (
+    payload => (others => '0'),
+    write_enable_out => '0',
+    is_full_in => '0'
+  ));
+  signal cpu_to_controller: cpu_to_controller_t := (
+    driver_id => (others => '0'),
+    address => (others => '0'),
+    seq_mem_access_count => 0,
+    cmd => "00"
+  );
+  signal drivers_to_controller: drivers_to_controller_t := (socbridge => (is_active => '0'));
+  signal controller_to_cpu: controller_to_cpu_t;
+  signal controller_to_drivers: controller_to_drivers_t;
+
+  signal curr_word : std_logic_vector(ext_to_ganimede.socbridge.payload'length - 1 downto 0);
+  signal expected_out : std_logic_vector(ganimede_to_ext.socbridge.payload'length - 1 downto 0);
+
+  procedure fail(error_msg : string) is 
+  begin
+    wait for CLK_PERIOD;
+    report "Simulation ending due to: " & error_msg & ". Shutting down..." severity FAILURE;
+  end procedure;
+
+  procedure check_next_state(correct_state: state_t) is
+  begin
+    if(not (correct_state = G_next_state)) then
+      report "Next State is not what was expected, found " & state_t'image(G_next_state)
+            & " but expected " & state_t'image(correct_state) severity error;
+      fail("Next State");
+    end if;
+  end procedure;
+  
+  procedure check_data_out(correct_data: std_logic_vector(ganimede_to_ext.socbridge.payload'length - 1 downto 0)) is
+  begin
+    if(not (correct_data = ganimede_to_ext.socbridge.payload)) then
+      report "Data out is not what was expected, found " & to_string(ganimede_to_ext.socbridge.payload)
+            & " but expected " & to_string(correct_data) severity error;
+      fail("Data out");
+    end if;
+  end procedure;
+
+  procedure check_parity(correct_data: std_logic_vector(ganimede_to_ext.socbridge.payload'length - 1 downto 0)) is
+  begin
+    if(not (calc_parity(correct_data) = calc_parity(ganimede_to_ext.socbridge.payload))) then
+      report "Parity out is not what was expected, found " & std_logic'image(calc_parity(ganimede_to_ext.socbridge.payload))
+            & " but expected " & std_logic'image(calc_parity(correct_data))  severity error;
+      fail("Parity out");
+    end if;
+  end procedure;
+
+begin
+  ganimede_inst: entity ganimede.ganimede_toplevel
+    port map(
+      clk                    => clk,
+      rst                    => rst,
+      cpu_to_ganimede        => cpu_to_ganimede,
+      ganimede_to_cpu        => ganimede_to_cpu,
+      ext_to_ganimede        => ext_to_ganimede,
+      ganimede_to_ext        => ganimede_to_ext,
+      ip_to_ganimede         => ip_to_ganimede,
+      ganimede_to_ip         => ganimede_to_ip
+    );
+  
+  ext_to_ganimede.socbridge.control(1) <= clk;
+  controller_clock_proc: process
+  begin
+  for i in 0 to SIMULATION_CYCLE_COUNT - 1 loop
+    wait for CLK_PERIOD / 2;
+    clk <= not clk;
+  end loop;
+  wait;
+  end process controller_clock_proc;
+  
+  stimulus_proc: process
+  begin
+    report "Starting Simulation Stimulus!";
+    rst <= '1';
+    cpu_to_controller.address <= (others => '0');
+    cpu_to_controller.cmd <= "00";
+    cpu_to_controller.driver_id <= "1";
+    cpu_to_controller.seq_mem_access_count <= 256;
+    wait for 3 * CLK_PERIOD;
+    report "Reset grace period ended, starting stimulus...";
+    rst <= '0';
+    cpu_to_controller.address <= x"FA0FA0FA";
+    cpu_to_controller.cmd <= "01";
+    wait until drivers_to_controller.socbridge.is_active = '1';
+    report "Task received in driver, awaiting completion...";
+    cpu_to_controller.address <= (others => '0');
+    cpu_to_controller.cmd <= "00";
+    wait until drivers_to_controller.socbridge.is_active = '0';
+    wait for CLK_PERIOD;
+    report "Task completed in driver, sending next task...";
+    cpu_to_controller.address <= x"FA0FA0FA";
+    cpu_to_controller.cmd <= "10";
+    wait for CLK_PERIOD;
+    wait until drivers_to_controller.socbridge.is_active = '1';
+    report "Task received in driver, awaiting completion...";
+    cpu_to_controller.address <= (others => '0');
+    cpu_to_controller.cmd <= "00";
+    wait until drivers_to_controller.socbridge.is_active = '0';
+    wait for CLK_PERIOD;
+    report "Task completed in driver, ending simulation stimulus";
+    cpu_to_controller.address <= (others => '0');
+    cpu_to_controller.cmd <= "00";
+    cpu_to_controller.driver_id <= "0";
+    cpu_to_controller.seq_mem_access_count <= 0;
+
+    wait;
+  end process stimulus_proc;
+
+  external_stimulus_signal: process(curr_word)
+  begin
+    ext_to_ganimede.socbridge.payload <= curr_word;
+    ext_to_ganimede.socbridge.control(0) <= calc_parity(curr_word);
+  end process external_stimulus_signal;
+
+  external_stimulus: process
+    variable input : positive := 1;
+  begin
+    wait for CLK_PERIOD / 1000;
+    curr_word <= "00000000"; 
+    wait for 999 * CLK_PERIOD / 1000;
+    wait for 2 * CLK_PERIOD;
+    wait for CLK_PERIOD / 2;
+    wait for 10* CLK_PERIOD;
+    curr_word <= "00001001";
+    wait for CLK_PERIOD;
+    curr_word <= "00000000";
+    wait for CLK_PERIOD * 140;
+    curr_word <= "00101001";
+    wait for CLK_PERIOD;
+    curr_word <= "00000000";
+    wait for CLK_PERIOD * 140;
+    curr_word <= "00101001";
+    wait for CLK_PERIOD;
+    curr_word <= "00000000";
+    wait for CLK_PERIOD * 20;
+    curr_word <= "01100111";
+    wait for CLK_PERIOD;
+    for x in 0 to 127 loop
+      curr_word <= std_logic_vector(to_unsigned(input, 8));
+      input := input + 1 mod 256;
+      wait for CLK_PERIOD;
+    end loop;
+    curr_word <= "00000000";
+    wait for CLK_PERIOD * 140;
+    wait for CLK_PERIOD * 20;
+    curr_word <= "01100111";
+    wait for CLK_PERIOD;
+    for x in 0 to 127 loop
+      curr_word <= std_logic_vector(to_unsigned(input, 8));
+      input := input + 1 mod 256;
+      wait for CLK_PERIOD;
+    end loop;
+
+    wait;
+  end process external_stimulus;
+
+  internal_stimulus: process
+    variable input : positive := 1;
+  begin
+    ip_to_ganimede.socbridge.is_full_in <= '0';
+    ip_to_ganimede.socbridge.write_enable_out <= '0';
+    wait for 3 * CLK_PERIOD;
+    -- stimulus goes here
+    ip_to_ganimede.socbridge.write_enable_out <= '1';
+    ip_to_ganimede.socbridge.payload <= std_logic_vector(to_unsigned(input, ip_to_ganimede.socbridge.payload'length));
+    input := input + 1 mod 256;
+    wait until rising_edge(clk) and ganimede_to_ip.socbridge.is_full_out = '0';
+    wait until falling_edge(clk);
+    for x in 0 to 1000 loop
+      ip_to_ganimede.socbridge.payload <= std_logic_vector(to_unsigned(input, ip_to_ganimede.socbridge.payload'length));
+      input := input + 1 mod 256;
+      wait until rising_edge(clk) and ganimede_to_ip.socbridge.is_full_out = '0';
+      wait until falling_edge(clk);
+    end loop;
+    wait;
+  end process internal_stimulus;
+
+end architecture tb;

src/ganimede/io_type_pkg.vhd

@@ -5,64 +5,52 @@ use IEEE.MATH_REAL.all;
 package io_types is
   
   --- CONSTANTS ---
-  constant number_of_drivers: natural := 1;
-  constant address_width: natural := 32;
-  constant seq_vector_length: natural := 8;
-  constant inst_word_width: natural := 2;
+  constant number_of_drivers : natural := 1;
+  constant address_width     : natural := 32;
+  constant inst_word_width   : natural := 2;
 
   --- STANDARD TYPES ---
   type instruction_command_t is (NO_OP, READ, WRITE);
 
   type ext_protocol_def_t is record
     name: string (1 to 20);
-    payload_width: natural;
-    control_width_in, control_width_out: natural;
+    payload_width                       : natural;
+    control_width_in, control_width_out : natural;
   end record ext_protocol_def_t;
 
   type interface_inst_t is record
-    socbridge: ext_protocol_def_t;
+    socbridge : ext_protocol_def_t;
   end record interface_inst_t;
 
   --- CONTROL UNIT ---
-  type cpu_to_controller_t is record
-    driver_id: std_logic_vector(number_of_drivers - 1 downto 0);
-    address: std_logic_vector(address_width - 1 downto 0);
-    seq_mem_access_count: integer;
-    cmd: std_logic_vector(1 downto 0);
-  end record cpu_to_controller_t;
+  type manager_to_controller_t is record
+    driver_id            : std_logic_vector(number_of_drivers - 1 downto 0);
+    address              : std_logic_vector(address_width - 1 downto 0);
+    seq_mem_access_count : integer;
+    cmd                  : std_logic_vector(1 downto 0); --Noop: 00; Write: 01; Read: 10 
+  end record manager_to_controller_t;
 
-  type controller_to_cpu_t is record
-    ready: std_logic;
-  end record controller_to_cpu_t;
-
-  --type controller_to_socbridge_driver_t is record
-  --  driver_id: std_logic_vector(number_of_drivers - 1 downto 0);
-  --  address: std_logic_vector(address_width - 1 downto 0);
-  --  seq_mem_access_count: integer;
-  --  instruction: instruction_command_t;
-  --end record controller_to_socbridge_driver_t;
-
-  --type socbridge_driver_to_controller_t is record
-  --  active_driver: std_logic_vector(number_of_drivers - 1 downto 0);
-  --end record socbridge_driver_to_controller_t;
-
-  type socbridge_driver_to_controller_t is record
-    is_active : std_logic;    
-  end record socbridge_driver_to_controller_t;
-
-  type controller_to_socbridge_driver_t is record
-    request: std_logic;
-    address: std_logic_vector(address_width - 1 downto 0);
-    seq_mem_access_count: integer;
-    instruction: instruction_command_t;
-  end record controller_to_socbridge_driver_t;
+  type controller_to_manager_t is record
+    ready : std_logic;
+  end record controller_to_manager_t;
 
   --- PROTOCOL INFORMATION ---
   constant interface_inst : interface_inst_t := (
     socbridge => ("SoCBridge           ", 8, 2, 2)
-  ); 
+  );
 
   --- AUTOGENERATED TYPES ---
+  type socbridge_driver_to_controller_t is record
+    is_active : std_logic;
+  end record socbridge_driver_to_controller_t;
+
+  type controller_to_socbridge_driver_t is record
+    request              : std_logic;
+    address              : std_logic_vector(address_width - 1 downto 0);
+    seq_mem_access_count : integer;
+    instruction          : instruction_command_t;
+  end record controller_to_socbridge_driver_t;
+
   type ext_to_socbridge_driver_t is record 
     payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
     control : STD_LOGIC_VECTOR(interface_inst.socbridge.control_width_in - 1 downto 0);
@@ -73,30 +61,38 @@ package io_types is
     control : STD_LOGIC_VECTOR(interface_inst.socbridge.control_width_in - 1 downto 0);
   end record socbridge_driver_to_ext_t;
 
-  type socbridge_driver_to_buffer_t is record 
+  type socbridge_driver_to_ip_t is record 
     payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
     write_enable_in, is_full_out : std_logic;
-  end record socbridge_driver_to_buffer_t;
+  end record socbridge_driver_to_ip_t;
 
-  type buffer_to_socbridge_driver_t is record 
+  type ip_to_socbridge_driver_t is record 
     payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
     write_enable_out, is_full_in : std_logic;
-  end record buffer_to_socbridge_driver_t;
+  end record ip_to_socbridge_driver_t;
 
-  type ext_interface_in_t is record
-    socbridge : ext_to_socbridge_driver_t;     
-  end record ext_interface_in_t;
+  type controller_to_drivers_t is record
+    socbridge : controller_to_socbridge_driver_t;
+  end record controller_to_drivers_t;
 
-  type ext_interface_out_t is record
+  type drivers_to_controller_t is record
+    socbridge : socbridge_driver_to_controller_t;
+  end record drivers_to_controller_t;
+
+  type ext_to_ganimede_t is record
+    socbridge : ext_to_socbridge_driver_t;
+  end record ext_to_ganimede_t;
+
+  type ganimede_to_ext_t is record
     socbridge : socbridge_driver_to_ext_t;
-  end record ext_interface_out_t;
+  end record ganimede_to_ext_t;
 
-  type int_interface_out_t is record
-    socbridge : socbridge_driver_to_buffer_t;
-  end record int_interface_out_t;
+  type ganimede_to_ip_t is record
+    socbridge : socbridge_driver_to_ip_t;
+  end record ganimede_to_ip_t;
 
-  type int_interface_in_t is record
-    socbridge : buffer_to_socbridge_driver_t;
-  end record int_interface_in_t;
+  type ip_to_ganimede_t is record
+    socbridge : ip_to_socbridge_driver_t;
+  end record ip_to_ganimede_t;
 
 end package io_types;

src/gantry.toml

@@ -0,0 +1,189 @@
+title = "ganimede"
+createdAt = "2025-03-14"
+maintainer = ""
+email = ""
+version = "0.0.1"
+
+[libraries.gan_socbridge]
+vhdl-version = "93c"
+path = "socbridge"
+
+[libraries.ganimede]
+vhdl-version = "93c"
+path = "ganimede"
+
+[libraries.controller]
+vhdl-version = "93c"
+path = "controller"
+
+[libraries.testbenches]
+vhdl-version = "93c"
+path = "control_socbridge_merge"
+
+[libraries.gaisler]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/gaisler"
+
+[libraries.grlib]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/grlib"
+
+[libraries.gr_socbridge_tb]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/verification/socbridge"
+
+[libraries.techmap]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/gencomp"
+
+[libraries.alltech]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/alltech"
+
+[libraries.altera_mf]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/altera_mf"
+
+[libraries.apa]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/apa"
+
+[libraries.artisan]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/artisan"
+
+[libraries.atc18]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/atc18"
+
+[libraries.axcelerator]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/axcelerator"
+
+[libraries.cust1]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/cust1"
+
+[libraries.cycloneiii]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/cycloneiii"
+
+[libraries.dware]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/dware"
+
+[libraries.ec]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/ec"
+
+[libraries.eclipsee]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/eclipsee"
+
+[libraries.fusion]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/fusion"
+
+[libraries.inferred]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/inferred"
+
+[libraries.grdware]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/grdware"
+
+[libraries.maps]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/maps"
+
+[libraries.nx]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/nx"
+
+[libraries.polarfire]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/polarfire"
+
+[libraries.nexus]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/nexus"
+
+[libraries.proasic3]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/proasic3"
+
+[libraries.proasic3e]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/proasic3e"
+
+[libraries.proasic3l]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/proasic3l"
+
+[libraries.saed32]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/saed32"
+
+[libraries.smartfusion2]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/smartfusion2"
+
+[libraries.stratixiii]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/stratixiii"
+
+[libraries.stratixii]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/stratixii"
+
+[libraries.stratixiv]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/stratixiv"
+
+[libraries.stratixv]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/stratixv"
+
+[libraries.umc18]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/umc18"
+
+[libraries.unisim]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/unisim"
+
+[libraries.virage90]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/virage90"
+
+[libraries.virage]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/virage"
+
+[libraries.virtex]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/virtex"
+
+[libraries.virtex5]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/techmap/virtex5"
+
+[libraries.opencores]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/opencores"
+
+[libraries.eth]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/eth"
+
+[libraries.micron]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/lib/micron"
+
+[libraries.ahb2ahb]
+vhdl-version = "93c"
+path = "grlib-com-nx-2024.4-b4295/verification/ahb2ahb"
+
+[libraries.manager]
+vhdl-version = "93c"
+path = "manager"

src/manager/management_unit.vhd

@@ -0,0 +1,86 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.MATH_REAL.all;
+use ieee.numeric_std.all;
+library manager;
+use manager.management_types.all;
+library ganimede;
+use ganimede.io_types.all;
+
+entity management_unit is
+  port (
+    clk, rst                    : in std_logic;
+    manager_to_controller       : out manager_to_controller_t;
+    controller_to_manager       : in controller_to_manager_t; 
+    socbridge_driver_to_manager : in socbridge_driver_to_manager_t;
+    manager_to_socbridge_driver : out manager_to_socbridge_driver_t 
+  );
+
+end entity management_unit;
+
+architecture rtl of management_unit is
+  signal manager_state : manager_state_t;
+  signal write_address : manager_word_t;
+  signal read_address  : manager_word_t;
+  signal msg_size      : manager_word_t;
+  -- Address indexing whole words, not bytes
+  signal word_address  : natural;
+begin
+
+word_address  <= to_integer(shift_right(unsigned(socbridge_driver_to_manager.address), address_shift));
+read_address  <= manager_state.memory(word_address);
+write_address <= manager_state.memory(word_address);
+
+
+comb_proc: process(controller_to_manager, socbridge_driver_to_manager)
+begin
+  -- Read data from manager to SoCBridge driver
+  manager_to_socbridge_driver.ready <= '1';
+  manager_to_socbridge_driver.data <= manager_state.memory(word_address);
+  manager_to_socbridge_driver.valid <= '1';
+end process comb_proc;
+
+-- tre sorters sätt att avsluta en skrivning:
+-- timeout om vi villha det
+-- en lastbit genooom axi interface
+-- vi har fått all data vi begärde.
+
+seq_proc: process(clk)
+begin
+  if rising_edge(clk) then
+    if rst = '1' then
+      manager_state <= manager_state_reset_val;
+    else
+      -- Write data from SoCBridge driver to address
+      if socbridge_driver_to_manager.valid = '1' then
+        manager_state.memory(word_address) <= socbridge_driver_to_manager.data;
+        if socbridge_driver_to_manager.address = read_address_index
+        or socbridge_driver_to_manager.address = write_address_index then
+          -- CLEAR BUFFER TO IP CORE
+        end if;
+      end if;
+
+      -- Is there a read instruction in memory
+      if read_address /= empty_word and controller_to_manager.ready = '1' then
+        manager_to_controller.address <= read_address;
+        manager_to_controller.driver_id <= "1"; -- Only supprts one driver at present
+        manager_to_controller.seq_mem_access_count <= to_integer(unsigned(msg_size));
+        manager_to_controller.cmd <= "10";
+      -- Is there a write instruction in memory
+      elsif write_address /= empty_word and controller_to_manager.ready = '1' then
+        manager_to_controller.address <= write_address;
+        manager_to_controller.driver_id <= "1"; -- Only supports one driver at present
+        manager_to_controller.seq_mem_access_count <= to_integer(unsigned(msg_size));
+        manager_to_controller.cmd <= "01";
+      else
+      -- No instruction present in memory, all zeroes to control unit
+        manager_to_controller.address <= (others => '0');
+        manager_to_controller.driver_id <= "0"; -- Only supprts one driver at present
+        manager_to_controller.seq_mem_access_count <= 0;
+        manager_to_controller.cmd <= "00";
+      end if;
+    end if;
+  end if;
+end process seq_proc;
+
+end architecture rtl ;

src/manager/management_unit_pkg.vhd

@@ -0,0 +1,45 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.MATH_REAL.all;
+library ganimede;
+use ganimede.io_types.all;
+
+package management_types is
+  constant WORD_SIZE : natural := 32;
+  -- Amount to right shift addres to convert e.g 0x00000004 to 0x00000001 for 32-bit words
+  constant address_shift : natural := natural(FLOOR(LOG2(real(WORD_SIZE) / real(8))));
+  subtype manager_word_t is std_logic_vector(WORD_SIZE - 1 downto 0);
+  constant empty_word : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0');
+  constant mem_words : natural := 64;
+  type memory_t is array (0 to mem_words - 1) of manager_word_t;
+
+  -- Index in memory array where memory read address is kept.
+  -- Read is active while it is not all zero.
+  constant read_address_index  : std_logic_vector(WORD_SIZE - 1 downto 0) := x"00000000";
+  -- Index in memory array where memory write address is kept.
+  -- Write is active while it is not all zero. Mutex with read address
+  constant write_address_index : std_logic_vector(WORD_SIZE - 1 downto 0) := x"00000001";
+  constant access_size         : std_logic_vector(WORD_SIZE - 1 downto 0) := x"00000002";
+
+  -- Status register for debugging
+  type manager_state_t is record
+    memory : memory_t;
+    data_out : manager_word_t;
+  end record manager_state_t;
+
+  -- reset value of status register
+  constant manager_state_reset_val : manager_state_t := ((others => (others => '0')), x"00000000");
+
+  type socbridge_driver_to_manager_t is record
+    address : manager_word_t;
+    data : manager_word_t;
+    valid: std_logic;
+  end record socbridge_driver_to_manager_t;
+
+  type manager_to_socbridge_driver_t is record
+    data : manager_word_t;
+    valid : std_logic;
+    ready : std_logic;
+  end record manager_to_socbridge_driver_t;
+
+end package;

src/manager/management_unit_tb.vhd

@@ -0,0 +1,124 @@
+library IEEE;  
+use IEEE.std_logic_1164.all;
+use IEEE.MATH_REAL.all;
+use IEEE.numeric_std.all;
+library ganimede;
+use ganimede.io_types.all;
+library manager;
+use manager.management_types.all;
+
+entity management_unit_tb is
+end entity management_unit_tb;
+
+architecture tb of management_unit_tb is
+  signal clk : std_logic := '0';
+  signal rst : std_logic;
+  
+  signal manager_to_controller       : manager_to_controller_t;       
+  signal controller_to_manager       : controller_to_manager_t := (ready => '0'); 
+  signal socbridge_driver_to_manager : socbridge_driver_to_manager_t := (
+    address => (others => '0'),
+    data => (others => '0'),
+    valid => '0'
+  );
+  signal manager_to_socbridge_driver : manager_to_socbridge_driver_t; 
+
+  constant halfcycle: Time := 5 ns;
+  constant cycle: Time := 2 * halfcycle;
+
+  function to_string ( a: std_logic_vector) return string is
+  variable b : string (1 to a'length) := (others => NUL);
+  variable stri : integer := 1; 
+  begin
+      for i in a'range loop
+          b(stri) := std_logic'image(a((i)))(2);
+      stri := stri+1;
+      end loop;
+  return b;
+  end function;
+
+begin
+  
+  clock_proc: process
+  begin
+  for i in 0 to 50 loop
+    wait for halfcycle;
+    clk <= not clk;
+  end loop;
+  wait;
+  end process clock_proc;
+
+  management_unit_inst: entity manager.management_unit
+    port map(
+    clk             => clk,
+    rst             => rst,
+    manager_to_controller       => manager_to_controller,
+    controller_to_manager       => controller_to_manager, 
+    socbridge_driver_to_manager => socbridge_driver_to_manager,
+    manager_to_socbridge_driver => manager_to_socbridge_driver 
+    );
+  
+tb_proc: process
+begin
+  controller_to_manager.ready <= '0'; 
+  rst <= '1';
+  wait for cycle;
+  rst <= '0';
+
+  report "Testing write to 0x00000014";
+  socbridge_driver_to_manager.data <= x"FA0FA0FA";
+  socbridge_driver_to_manager.address <= x"00000014";
+  socbridge_driver_to_manager.valid <= '1';
+  wait for cycle;
+  socbridge_driver_to_manager.valid <= '0';
+  socbridge_driver_to_manager.data <= x"00000000";
+  socbridge_driver_to_manager.address <= x"00000000";
+  wait for halfcycle;
+  assert manager_to_socbridge_driver.data = x"FA0FA0FA" report "Write to address 0x00000005 failed! expected 0xFA0FA0FA but got " & natural'image(to_integer(unsigned(manager_to_socbridge_driver.data))) severity error;
+
+  wait for 5 * cycle;
+
+  report "Testing submission of write instruction of 10 words to address 0x40000000";
+  controller_to_manager.ready <= '1';
+  socbridge_driver_to_manager.data <= x"40000000";
+  socbridge_driver_to_manager.address <= x"00000004";
+  socbridge_driver_to_manager.valid <= '1';
+  wait for cycle;
+  socbridge_driver_to_manager.data <= x"0000000A";
+  socbridge_driver_to_manager.address <= x"00000008";
+  socbridge_driver_to_manager.address <= x"00000000";
+  socbridge_driver_to_manager.valid <= '1';
+  wait for cycle;
+  socbridge_driver_to_manager.valid <= '0';
+  socbridge_driver_to_manager.data <= x"00000000";
+  wait for cycle;
+  controller_to_manager.ready <= '1';
+  wait for halfcycle;
+  assert manager_to_controller.address = x"40000000" report "Controller got the wrong address! Expected 0x40000000 but got " & to_string(manager_to_controller.address) severity error;
+  assert manager_to_controller.cmd = "10" report "Controller got the wrong command! Expected 0b10 but got " & to_string(manager_to_controller.cmd) severity error;  
+  assert manager_to_controller.seq_mem_access_count = 10 report "Controller got the wrong message size! expected 10 but got " & natural'image(manager_to_controller.seq_mem_access_count) severity error;  
+
+  wait for 5 * cycle;
+  controller_to_manager.ready <= '0'; 
+
+  report "Testing submission of read instruction of 20 words from address 0x50000000";
+  socbridge_driver_to_manager.data <= x"50000000";
+  socbridge_driver_to_manager.address <= x"00000000";
+  socbridge_driver_to_manager.valid <= '1';
+  wait for cycle;
+  socbridge_driver_to_manager.data <= x"00000014";
+  socbridge_driver_to_manager.address <= x"00000008";
+  socbridge_driver_to_manager.valid <= '1';
+  wait for cycle;
+  socbridge_driver_to_manager.valid <= '0';
+  socbridge_driver_to_manager.address <= x"00000000";
+  socbridge_driver_to_manager.data <= x"00000000";
+  controller_to_manager.ready <= '1';
+  wait for halfcycle;
+  assert manager_to_controller.address = x"50000000" report "Controller got the wrong address! Expected 0x50000000 but got " & to_string(manager_to_controller.address) severity error;
+  assert manager_to_controller.cmd = "01" report "Controller got the wrong command! Expected 0b01 but got " & to_string(manager_to_controller.cmd) severity error;  
+  assert manager_to_controller.seq_mem_access_count = 20 report "Controller got the wrong message size! expected 20 but got " & natural'image(manager_to_controller.seq_mem_access_count) severity error;  
+  wait;
+end process tb_proc;
+  
+end architecture tb ;

src/socbridge/socbridge_driver.vhd

@@ -3,11 +3,14 @@ use IEEE.std_logic_1164.all;
 use IEEE.NUMERIC_STD.all;
 library ganimede;
 use ganimede.io_types.all;
-library socbridge;
-use socbridge.socbridge_driver_tb_pkg.all;
+library gan_socbridge;
+use gan_socbridge.socbridge_driver_tb_pkg.all;
 
 
 entity socbridge_driver is
+  generic(
+    MAX_PKT_SIZE : integer range 1 to 128 := 32
+         );
   port(
     clk                            : in std_logic;
     rst                            : in std_logic;
@@ -15,8 +18,8 @@ entity socbridge_driver is
     socbridge_driver_to_controller : out socbridge_driver_to_controller_t;
     ext_to_socbridge_driver        : in ext_to_socbridge_driver_t;
     socbridge_driver_to_ext        : out socbridge_driver_to_ext_t;
-    socbridge_driver_to_buffer     : out socbridge_driver_to_buffer_t;
-    buffer_to_socbridge_driver     : in buffer_to_socbridge_driver_t
+    ip_to_socbridge_driver         : in ip_to_socbridge_driver_t;
+    socbridge_driver_to_ip         : out socbridge_driver_to_ip_t
   );
 end entity socbridge_driver;
 
@@ -25,12 +28,13 @@ architecture rtl of socbridge_driver is
   signal next_parity_out                           : std_logic;
   signal ext_to_socbridge_driver_rec               : ext_protocol_t;
   shared variable socbridge_driver_to_ext_data_cmd : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
+  shared variable next_rx_transaction                   : transaction_t;
+  shared variable next_tx_transaction                   : transaction_t;
   signal test                                      : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
-  signal next_cmd                                  : command_t;
   signal next_cmd_size                             : integer;
-  signal next_state                                : state_t;
+  signal next_rx_state                             : rx_state_t;
+  signal next_tx_state                             : tx_state_t;
   signal curr_cmd_bits                             : std_logic_vector(4 downto 0);
-  signal curr_response                             : response_t;
   signal curr_response_bits                        : std_logic_vector(4 downto 0);
   signal st                                        : state_rec_t;
   --- TRANSLATOR ---
@@ -41,10 +45,8 @@ begin
   -- synthesis translate_off
   G_next_parity_out <= next_parity_out;
   G_ext_to_socbridge_driver_rec <= ext_to_socbridge_driver_rec;
-  G_next_state <= next_state;
   G_socbridge_driver_to_ext_data_cmd <=test;
   G_curr_command_bits <= curr_cmd_bits;
-  G_curr_response <= curr_response;
   G_curr_response_bits <= curr_response_bits;
   G_st <= st;
   G_trans_st <= trans_st;
@@ -71,176 +73,225 @@ begin
                                                     -- 00001     | 00001001   | 00001001 
                                                     -- 00001     | 00001001   | 00001001 
                                                   
-  with curr_response_bits select
-    curr_response <= WRITE_ACK when "00001",
-                      WRITE_ACK when "00101",
-                      READ_RESPONSE when "01000",
-                      READ_RESPONSE when "01100",
-                      NO_OP when others;
-  comb_proc: process(ext_to_socbridge_driver, buffer_to_socbridge_driver, curr_response, st, controller_to_socbridge_driver, trans_st)
+  comb_proc: process(ext_to_socbridge_driver, ip_to_socbridge_driver, st, controller_to_socbridge_driver, trans_st)
   begin
     -- Outputs 
     socbridge_driver_to_ext <= create_io_type_out_from_ext_protocol(st.socbridge_driver_to_ext_reg);
-    with trans_st.curr_state select
-    socbridge_driver_to_controller.is_active <= '0' when IDLE,
-                          '1' when others;
 
-    --- State Transition Diagram ---
---                                                            
---                                               
---                                               
---           +-----+                                     
---           |     |                                             
---          \|/ /--+                                             
---          IDLE<-------------------+                 
---          /  \                    |                            
---         /     \                  |                            
---        /       \                 |                            
---      \|/       \|/               |                         
---  TX_HEADER   RX_HEADER           |                        
---       |\     /    |              |                           
---       | \   /     |              |                           
---       |  ADDR1    |              |                           
---       |    |      |              |                           
---       |   \|/     |              |                           
---       |  ADDR2    |              |                           
---       |    |      |              |                           
---       |   \|/     |              |                           
---       |  ADDR3    |              |                           
---       |    |      |              |                           
---       |   \|/     |              |                           
---       |  ADDR4    |              |                           
---       |   /\      |              |                           
---       |  /  \     |              |                           
---       |-+    +----|     +---+    |                           
---      \|/         \|/   \|/  |    |                           
---   TX_BODY     RX_RESPONSE---+    |                           
---       |           |              |                           
---       |  +--+     |              |                           
---      \|/\|/ |    \|/             |                           
---     TX_ACK--+ RX_BODY            |                           
---       |           |              |                           
---       |           |              |                           
---       +-----------+--------------+                 
---                                                            
-  --- Next State Assignment --- 
-    case st.curr_state is
+    -- Set helper var to current transaction seen at the input.
+    next_rx_transaction := NO_OP;
+    if curr_response_bits = "10000" then 
+      next_rx_transaction := WRITE_ADD;
+    elsif curr_response_bits = "10100" then
+      next_rx_transaction := WRITE;
+    elsif curr_response_bits = "11000" then
+      next_rx_transaction := READ_ADD;
+    elsif curr_response_bits = "11100" then
+      next_rx_transaction := READ;
+    elsif curr_response_bits = "01001" then -- TODO Might have to check bits 2:0
+      next_rx_transaction := P_ERR;
+    elsif curr_response_bits = "00101" then
+      next_rx_transaction := WRITE_ACK;
+    elsif curr_response_bits = "01100" then
+      next_rx_transaction := READ_RESPONSE;
+    end if;
+
+    if trans_st.curr_state = IDLE then
+      socbridge_driver_to_controller.is_active <= '0';
+    else 
+      socbridge_driver_to_controller.is_active <= '1';
+    end if;
+
+  --- Next State Assignment Of RX FSM --- 
+    case st.curr_rx_state is
       when IDLE => 
-        if st.curr_cmd = WRITE or st.curr_cmd = WRITE_ADD then
-          next_state <= TX_HEADER;
-        elsif st.curr_cmd = READ or st.curr_cmd = READ_ADD then
-          next_state <= RX_HEADER;
+        if st.curr_rx_transaction /= NO_OP then 
+          --next_rx_state <= TX_HEADER;
         else
-          next_state <= IDLE;
+          next_rx_state <= IDLE;
+        end if;
+      when RX_R_BODY =>
+      -- Here we want to stay in RX_R_BODY for the duration of a packet.
+        if st.rx_stage = 0 then
+          next_rx_state <= IDLE;
+        else
+          next_rx_state <= RX_R_BODY;
+        end if;
+      when ADDR1 =>
+      -- Transmits the entire address and returns to the appropriate
+        next_rx_state <= ADDR2;
+      when ADDR2 =>
+        next_rx_state <= ADDR3;
+      when ADDR3 =>
+        next_rx_state <= ADDR4;
+      when ADDR4 =>
+        if next_rx_transaction = WRITE_ADD then 
+          next_rx_state <= RX_R_BODY;
+        elsif next_rx_transaction = READ_ADD then
+          --next_rx_state <= TELL_TX_TO_SEND_A_READ_RESPONSE;
+        else
+          next_rx_state <= IDLE; -- Potentially superfluous safety
+        end if;
+    end case;
+    
+  --- Next State Assignments --- 
+    --- ### TX NEXT STATE ASSIGNMENTS ### ---
+    case st.curr_tx_state is
+      when IDLE =>
+        if next_tx_transaction = READ_ADD or next_tx_transaction = READ or 
+           next_tx_transaction = WRITE_ADD or next_tx_transaction = WRITE then
+          next_tx_state <= TX_HEADER;
+        -- Otherwise we are ready to send a response to a read.
+        elsif RESPONSE_READY then -- TODO define RESPONSE_READY
+          -- IMMEDIATLY GO INTO CORRECT STATE?
+          --next_tx_state <= RESPONSE;
+        else 
+          next_tx_state <= IDLE;
+        end if;
+      when RESPONSE =>
+      -- TODO consider whether this should be moved to TX_W_BODY
+        if st.tx_stage = 0 then
+          next_tx_state <= IDLE;
+        else
+          next_tx_state <= RESPONSE;
         end if;
       when TX_HEADER =>
       -- The header only takes one word (cycle) to transmit.
       -- Continue to body or address directly afterwards. 
-        if st.curr_cmd = WRITE_ADD then
-          next_state <= ADDR1;
+        if st.curr_tx_transaction = WRITE_ADD then
+          next_tx_state <= ADDR1;
         else 
-          next_state <= TX_BODY;
+          next_tx_state <= TX_W_BODY;
         end if;
-      when TX_BODY =>
-      -- Here we want to stay in TX_BODY for the duration of a packet.
-        if st.write_stage = 0 then
-          next_state <= TX_ACK;
+      when TX_W_BODY =>
+      -- Here we want to stay in TX_W_BODY for the duration of a packet.
+        if st.tx_stage = 0 then
+          next_tx_state <= TX_AWAIT;
         else 
-          next_state <= TX_BODY;
-        end if;
-      when TX_ACK =>
-      -- Wait for write acknowledgement. 
-        if curr_response = WRITE_ACK then
-          next_state <= IDLE;
-        else 
-          next_state <= TX_ACK;
-        end if;
-      when RX_HEADER =>
-      -- The header only takes one word (cycle) to transmit.
-      -- Continue to awaiting response directly afterwards.
-        if st.curr_cmd = READ_ADD then
-          next_state <= ADDR1;
-        else 
-          next_state <= RX_RESPONSE;
-        end if;
-      when RX_RESPONSE =>
-      -- Wait for read response. 
-        if curr_response = READ_RESPONSE then
-          next_state <= RX_BODY;
-        else 
-          next_state <= RX_RESPONSE;
-        end if;
-      when RX_BODY =>
-      -- Here we want to stay in RX_BODY for the duration of a packet.
-        if st.read_stage = 0 then
-          next_state <= IDLE;
-        else 
-          next_state <= RX_BODY;
+          next_tx_state <= TX_W_BODY;
         end if;
       when ADDR1 =>
       -- Transmits the entire address and returns to the appropriate 
-        next_state <= ADDR2;
+        next_tx_state <= ADDR2;
       when ADDR2 =>
-        next_state <= ADDR3;
+        next_tx_state <= ADDR3;
       when ADDR3 =>
-        next_state <= ADDR4;
+        next_tx_state <= ADDR4;
       when ADDR4 => 
-        if st.curr_cmd = WRITE or st.curr_cmd = WRITE_ADD then 
-          next_state <= TX_BODY;
+        if st.curr_tx_transaction = WRITE or st.curr_tx_transaction = WRITE_ADD then 
+          next_tx_state <= TX_W_BODY;
         else 
-          next_state <= RX_RESPONSE;
+        -- If it is a read instruction we wait for response.
+        -- TODO separate read from NO_OP and P_ERR
+          next_tx_state <= TX_AWAIT;
+        end if;
+      when TX_AWAIT => 
+        -- Wait for RX FSM to get a response
+        if st.curr_rx_transaction = WRITE_ACK or st.curr_rx_transaction = READ_RESPONSE then
+          next_tx_state <= IDLE;
+        else 
+          next_tx_state <= TX_AWAIT;
         end if;
     end case;
-    
+    --- ### RX NEXT STATE ASSIGNMENTS ### ---
+    case st.curr_rx_state is
+      when IDLE =>
+        -- Do we have a command, if so enter command state.
+        if next_rx_transaction = READ_ADD or next_rx_transaction = READ or 
+           next_rx_transaction = WRITE_ADD or next_rx_transaction = WRITE then
+          next_rx_state <= WRITE;
+        -- Otherwise we are ready to send a response to a read.
+        elsif RESPONSE_READY then -- TODO define RESPONSE_READY
+          -- SHOULD WE NOT MOVE TO CORRECT RESPONSE IMMEDIATLY?
+          next_rx_state <= RESPONSE;
+        else 
+          next_rx_state <= IDLE;
+        end if;
+      when RESPONSE =>
+      -- TODO consider whether this should be moved to rx_W_BODY
+        if st.rx_stage = 0 then
+          next_rx_state <= IDLE;
+        else
+          next_rx_state <= RESPONSE;
+        end if;
+      when RX_W_ACK =>
+        next_rx_state <= IDLE;
+      when RX_R_BODY => 
+      when ADDR1 =>
+        next_rx_state <= ADDR2;
+      when ADDR2 =>
+        next_rx_state <= ADDR3;
+      when ADDR3 =>
+        next_rx_state <= ADDR4;
+      when ADDR4 => 
+        if st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD then 
+          next_rx_state <= RX_R_BODY;
+        else 
+        -- If it is a read instruction we wait for response.
+        -- TODO separate read from NO_OP and P_ERR
+          --next_rx_state <= TX_AWAIT;
+        end if;
+    end case;
+
+
   --- Combinatorial output based on current state ---
     socbridge_driver_to_ext_data_cmd := (others => '0');
-    socbridge_driver_to_buffer.is_full_out <= '1';
-    socbridge_driver_to_buffer.write_enable_in <= '0';
-    socbridge_driver_to_buffer.payload <= (others => '0');
-    case st.curr_state is
+    socbridge_driver_to_ip.is_full_out <= '1';
+    socbridge_driver_to_ip.write_enable_in <= '0';
+    socbridge_driver_to_ip.payload <= (others => '0');
+    --- ### TX_STATE BASED OUTPUT ### ---
+    case st.curr_tx_state is
       when IDLE => 
-        if st.curr_cmd = WRITE or st.curr_cmd = WRITE_ADD then
-          socbridge_driver_to_ext_data_cmd := get_cmd_bits(st.curr_cmd) & get_size_bits(st.curr_cmd_size);
-        elsif st.curr_cmd = READ or st.curr_cmd = READ_ADD then
-          socbridge_driver_to_ext_data_cmd := get_cmd_bits(st.curr_cmd) & get_size_bits(st.curr_cmd_size);
+        if st.curr_tx_transaction = WRITE or st.curr_tx_transaction = WRITE_ADD then
+          socbridge_driver_to_ext_data_cmd := get_header_bits(st.curr_tx_transaction) & get_size_bits(st.curr_cmd_size);
+        elsif st.curr_tx_transaction = READ or st.curr_tx_transaction = READ_ADD then
+          socbridge_driver_to_ext_data_cmd := get_header_bits(st.curr_tx_transaction) & get_size_bits(st.curr_cmd_size);
         else
         end if;       
       when TX_HEADER =>
-        if st.curr_cmd = WRITE_ADD then
-          socbridge_driver_to_ext_data_cmd := st.curr_addr(7 downto 0);
+        if st.curr_tx_transaction = WRITE_ADD or st.curr_tx_transaction = READ_ADD then
+          socbridge_driver_to_ext_data_cmd := st.curr_addr(31 downto 24);
         else 
-          socbridge_driver_to_ext_data_cmd := buffer_to_socbridge_driver.payload;
-          socbridge_driver_to_buffer.is_full_out <= '0';
+          socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload;
+          socbridge_driver_to_ip.is_full_out <= '0';
         end if;
-      when TX_BODY =>
-        if st.write_stage > 0 then
-          socbridge_driver_to_buffer.is_full_out <= '0';
-          socbridge_driver_to_ext_data_cmd := buffer_to_socbridge_driver.payload;
+      when TX_W_BODY =>
+        if st.tx_stage > 0 then
+          socbridge_driver_to_ip.is_full_out <= '0';
+          socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload;
         else 
           socbridge_driver_to_ext_data_cmd := (others => '0');
         end if;
-      when TX_ACK =>
-      when RX_HEADER =>
-        if st.curr_cmd = READ_ADD then
-          socbridge_driver_to_ext_data_cmd := st.curr_addr(7 downto 0);
+      when TX_HEADER =>
+        if st.curr_tx_transaction = READ_ADD then
+          socbridge_driver_to_ext_data_cmd := st.curr_addr(31 downto 24);
         end if; 
-      when RX_RESPONSE =>
-      when RX_BODY =>
-        socbridge_driver_to_buffer.payload <= st.ext_to_socbridge_driver_reg.data;
-        socbridge_driver_to_buffer.write_enable_in <= '1';
+      when TX_AWAIT =>
       when ADDR1 =>
-        socbridge_driver_to_ext_data_cmd := st.curr_addr(15 downto 8);
-      when ADDR2 =>
         socbridge_driver_to_ext_data_cmd := st.curr_addr(23 downto 16);
+      when ADDR2 =>
+        socbridge_driver_to_ext_data_cmd := st.curr_addr(15 downto 8);
       when ADDR3 =>
-        socbridge_driver_to_ext_data_cmd := st.curr_addr(31 downto 24);
+        socbridge_driver_to_ext_data_cmd := st.curr_addr(7 downto 0);
       when ADDR4 =>
-        if st.curr_cmd = WRITE_ADD then
-          socbridge_driver_to_buffer.is_full_out <= '0';
-          socbridge_driver_to_ext_data_cmd := buffer_to_socbridge_driver.payload;
-          report integer'image(to_integer(signed(socbridge_driver_to_ext_data_cmd))) & " "&  integer'image(to_integer(signed(buffer_to_socbridge_driver.payload)));
+        if st.curr_tx_transaction = WRITE_ADD then
+          socbridge_driver_to_ip.is_full_out <= '0';
+          socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload;
+          report integer'image(to_integer(signed(socbridge_driver_to_ext_data_cmd))) & " "&  integer'image(to_integer(signed(ip_to_socbridge_driver.payload)));
         end if;
     end case;
+    --- ### RX_STATE BASED OUTPUT ### ---
+    case st.curr_rx_state is
+      when IDLE => 
+      when ADDR1 =>
+      when ADDR2 =>
+      when ADDR3 =>
+      when ADDR4 =>
+      when RX_W_ACK =>
+      when RX_R_BODY =>
+        socbridge_driver_to_ip.payload <= st.ext_to_socbridge_driver_reg.data;
+        socbridge_driver_to_ip.write_enable_in <= '1';
+    end case;
     next_parity_out <= calc_parity(socbridge_driver_to_ext_data_cmd);
     --- DEBUG GLOBAL BINDINGS ---
     -- synthesis translate_off
@@ -258,7 +309,7 @@ begin
         end if;
       -- Wait for driver to go idle and send next instruction. Then enter AWAIT
       when SEND =>
-        if st.curr_state /= IDLE then
+        if st.curr_tx_state /= IDLE then
           trans_next_state <= SEND_ACCEPTED;
         else 
           trans_next_state <= SEND;
@@ -268,9 +319,9 @@ begin
         trans_next_state <= AWAIT;
       -- Wait for driver to finish current instruction, then reenter SEND
       when AWAIT =>
-        if trans_st.curr_inst.seq_mem_access_count <= 0 and st.curr_state = IDLE then
+        if trans_st.curr_inst.seq_mem_access_count <= 0 and st.curr_tx_state = IDLE then
           trans_next_state <= IDLE;
-        elsif st.curr_state = IDLE then
+        elsif st.curr_tx_state = IDLE then
           trans_next_state <= SEND;
         else 
           trans_next_state <= AWAIT;
@@ -278,27 +329,27 @@ begin
     end case;
 
       --- Combinatorial output based on state
-    next_cmd <= NO_OP;
+    next_tx_transaction := NO_OP;
     next_cmd_size <= 0;
     case trans_st.curr_state is
       when IDLE =>
       when SEND =>
         if trans_st.is_first_word = '1' then 
           if trans_st.curr_inst.instruction = READ then
-            next_cmd <= READ_ADD;
+            next_tx_transaction := READ_ADD;
           elsif trans_st.curr_inst.instruction = WRITE then
-            next_cmd <= WRITE_ADD;
+            next_tx_transaction := WRITE_ADD;
           end if;
         else 
           if trans_st.curr_inst.instruction = READ then
-            next_cmd <= READ;
+            next_tx_transaction := READ;
           elsif trans_st.curr_inst.instruction = WRITE then
-            next_cmd <= WRITE;
+            next_tx_transaction := WRITE;
           end if;
         end if;
 
-        if trans_st.curr_inst.seq_mem_access_count > 128 then
-          next_cmd_size <= 128;
+        if trans_st.curr_inst.seq_mem_access_count > MAX_PKT_SIZE then
+          next_cmd_size <= MAX_PKT_SIZE;
         elsif trans_st.curr_inst.seq_mem_access_count > 0 then
           next_cmd_size <= trans_st.curr_inst.seq_mem_access_count;
         else 
@@ -316,10 +367,11 @@ begin
       st.socbridge_driver_to_ext_reg.data <= (others => '0');
       st.socbridge_driver_to_ext_reg.clk <= '0';
       st.socbridge_driver_to_ext_reg.parity <= '1';
-      st.curr_state <= IDLE;
-      st.write_stage <= 0;
-      st.read_stage <= 0;
-      st.curr_cmd <= NO_OP;
+      st.curr_tx_state <= IDLE;
+      st.curr_rx_state <= IDLE;
+      st.tx_stage <= 0;
+      st.rx_stage <= 0;
+      st.curr_tx_transaction <= NO_OP;
       st.curr_cmd_size <= 0;
       st.curr_addr <= (others => '0');
 
@@ -330,33 +382,36 @@ begin
       st.socbridge_driver_to_ext_reg.data <= socbridge_driver_to_ext_data_cmd;
       st.socbridge_driver_to_ext_reg.clk <= not st.socbridge_driver_to_ext_reg.clk;
       st.socbridge_driver_to_ext_reg.parity <= next_parity_out; 
-      st.curr_state <= next_state;
-      case st.curr_state is
+      st.curr_tx_state <= next_tx_state;
+      case st.curr_tx_state is
         when IDLE =>
-          st.curr_cmd <= next_cmd;   
+          st.curr_tx_transaction <= next_tx_transaction;   
           st.curr_cmd_size <= next_cmd_size;
           st.curr_addr <= trans_st.curr_inst.address;
           if next_cmd_size > 0 then
-            st.write_stage <= next_cmd_size - 1;
-            st.read_stage <= next_cmd_size - 1;
+            st.tx_stage <= next_cmd_size - 1;
+            st.rx_stage <= next_cmd_size - 1;
           end if;
         when TX_HEADER =>
-        when TX_BODY =>
-          if st.write_stage > 0 then
-            st.write_stage <= st.write_stage - 1;
+        when TX_W_BODY =>
+          if st.tx_stage > 0 then
+            st.tx_stage <= st.tx_stage - 1;
           end if;
-        when TX_ACK => 
-          st.curr_cmd <= NO_OP;
+        when others => 
+      end case;
+      case st.curr_rx_state is
+        when IDLE =>
+          st.curr_rx_transaction <= next_rx_transaction;   
+        when RX_W_ACK => 
+          st.curr_tx_transaction <= NO_OP;
           st.curr_cmd_size <= 0;
-        when RX_HEADER =>
-        when RX_BODY =>
-          if st.read_stage > 0 then
-            st.read_stage <= st.read_stage - 1;
+        when RX_R_BODY =>
+          if st.rx_stage > 0 then
+            st.rx_stage <= st.rx_stage - 1;
           else 
-            st.curr_cmd <= NO_OP;
+            st.curr_tx_transaction <= NO_OP;
             st.curr_cmd_size <= 0;
           end if;
-
         when others => 
       end case;
     end if;
@@ -381,9 +436,9 @@ begin
           trans_st.is_first_word <= '1';
         when SEND =>
         when SEND_ACCEPTED => 
-          trans_st.curr_inst.seq_mem_access_count <= trans_st.curr_inst.seq_mem_access_count - 128;
+          trans_st.curr_inst.seq_mem_access_count <= trans_st.curr_inst.seq_mem_access_count - MAX_PKT_SIZE;
         when AWAIT =>
-          if trans_st.curr_inst.seq_mem_access_count <= 0 and st.curr_state = IDLE then
+          if trans_st.curr_inst.seq_mem_access_count <= 0 and st.curr_tx_state = IDLE then
             trans_st.curr_inst.request <= '0';
             trans_st.curr_inst.address <= (others => '0');
             trans_st.curr_inst.seq_mem_access_count <= 0;

src/socbridge/socbridge_driver_tb.vhd

@@ -5,7 +5,7 @@ library work;
 use work.socbridge_driver_tb_pkg.all;
 library ganimede;
 use ganimede.io_types.all;
-library socbridge;
+library gan_socbridge;
 
 
 entity socbridge_driver_tb is
@@ -19,8 +19,8 @@ architecture tb of socbridge_driver_tb is
   signal cmd_size : positive;
   signal ext_to_socbridge_driver  :  ext_to_socbridge_driver_t;
   signal socbridge_driver_to_ext :  socbridge_driver_to_ext_t;
-  signal buffer_to_socbridge_driver  :  buffer_to_socbridge_driver_t;
-  signal socbridge_driver_to_buffer :  socbridge_driver_to_buffer_t;
+  signal ip_to_socbridge_driver  :  ip_to_socbridge_driver_t;
+  signal socbridge_driver_to_ip :  socbridge_driver_to_ip_t;
   signal controller_to_socbridge_driver :  controller_to_socbridge_driver_t;
   signal socbridge_driver_controller :  socbridge_driver_to_controller_t;
   signal curr_word : std_logic_vector(ext_to_socbridge_driver.payload'length - 1 downto 0);
@@ -71,8 +71,8 @@ architecture tb of socbridge_driver_tb is
 --      cmd_size: in positive;
 --      ext_to_socbridge_driver  : in ext_to_socbridge_driver_t;
 --      socbridge_driver_to_ext : out socbridge_driver_to_ext_t;
---      buffer_to_socbridge_driver  : out buffer_to_socbridge_driver_t;
---      socbridge_driver_to_buffer : in socbridge_driver_to_buffer_t
+--      ip_to_socbridge_driver  : out ip_to_socbridge_driver_t;
+--      socbridge_driver_to_ip : in socbridge_driver_to_ip_t
 --    );
 --  end component socbridge_driver;
 
@@ -85,8 +85,8 @@ begin
       socbridge_driver_to_controller => socbridge_driver_controller,
       ext_to_socbridge_driver => ext_to_socbridge_driver,
       socbridge_driver_to_ext => socbridge_driver_to_ext,
-      buffer_to_socbridge_driver => buffer_to_socbridge_driver,
-      socbridge_driver_to_buffer => socbridge_driver_to_buffer
+      ip_to_socbridge_driver => ip_to_socbridge_driver,
+      socbridge_driver_to_ip => socbridge_driver_to_ip
   );
 
   ext_to_socbridge_driver.control(1) <= clk;
@@ -299,30 +299,30 @@ begin
 
   internal_stimulus: process
   begin
-    buffer_to_socbridge_driver.is_full_in <= '0';
-    buffer_to_socbridge_driver.write_enable_out <= '0';
+    ip_to_socbridge_driver.is_full_in <= '0';
+    ip_to_socbridge_driver.write_enable_out <= '0';
     wait for 3 * CLK_PERIOD;
     -- stimulus goes here
-    buffer_to_socbridge_driver.write_enable_out <= '1';
-    buffer_to_socbridge_driver.payload <= "00000001";
-    wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0';
+    ip_to_socbridge_driver.write_enable_out <= '1';
+    ip_to_socbridge_driver.payload <= "00000001";
+    wait until rising_edge(clk) and socbridge_driver_to_ip.is_full_out = '0';
     wait until falling_edge(clk);
-    buffer_to_socbridge_driver.payload <= "00000010";
-    wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0';
+    ip_to_socbridge_driver.payload <= "00000010";
+    wait until rising_edge(clk) and socbridge_driver_to_ip.is_full_out = '0';
     wait until falling_edge(clk);
-    buffer_to_socbridge_driver.payload <= "00000100";
-    wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0';
+    ip_to_socbridge_driver.payload <= "00000100";
+    wait until rising_edge(clk) and socbridge_driver_to_ip.is_full_out = '0';
     wait until falling_edge(clk);
-    buffer_to_socbridge_driver.payload <= "00001000";
-    wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0';
+    ip_to_socbridge_driver.payload <= "00001000";
+    wait until rising_edge(clk) and socbridge_driver_to_ip.is_full_out = '0';
     wait until falling_edge(clk);
-    buffer_to_socbridge_driver.payload <= "00010000";
-    wait until socbridge_driver_to_buffer.is_full_out = '0';
+    ip_to_socbridge_driver.payload <= "00010000";
+    wait until socbridge_driver_to_ip.is_full_out = '0';
     wait for CLK_PERIOD/2;
     wait until rising_edge(clk);
     wait until rising_edge(clk);
-    buffer_to_socbridge_driver.payload <= "00100000";
-    wait until socbridge_driver_to_buffer.is_full_out = '0';
+    ip_to_socbridge_driver.payload <= "00100000";
+    wait until socbridge_driver_to_ip.is_full_out = '0';
     wait for CLK_PERIOD/2;
     wait until rising_edge(clk);
     wait until rising_edge(clk); --- ??? Why all these rising_edge checks?

src/socbridge/socbridge_driver_tb_pkg.vhd

@@ -9,17 +9,17 @@ use ganimede.io_types.all;
 package socbridge_driver_tb_pkg is
   subtype command_size_t is integer range 0 to 128;
 
-  type command_t is 
-    (NO_OP, WRITE_ADD, WRITE, READ_ADD, READ, P_ERR);
+  type transaction_t is
+    (NO_OP, WRITE_ADD, WRITE, READ_ADD, READ, P_ERR, WRITE_ACK, READ_RESPONSE);
 
-  type response_t is 
-    (NO_OP, WRITE_ACK, READ_RESPONSE);
-
-  type state_t is
-    (IDLE, ADDR1, ADDR2, ADDR3, ADDR4, 
-     TX_HEADER, TX_BODY, TX_ACK, 
-     RX_HEADER, RX_RESPONSE, RX_BODY);
+  type rx_state_t is
+    (IDLE, ADDR1, ADDR2, ADDR3, ADDR4, RX_AWAIT,
+     RESPONSE, READ, WRITE, PAYLOAD,
+     RX_W_ACK, RX_R_BODY, RX_HEADER, RX_W_BODY);
 
+  type tx_state_t is
+    (IDLE, ADDR1, ADDR2, ADDR3, ADDR4, TX_AWAIT, 
+     TX_HEADER, TX_W_BODY, TX_R_BODY, TX_W_ACK);
   --- TRANSLATOR ---
   type translator_state_t is (IDLE, SEND, SEND_ACCEPTED, AWAIT);
 
@@ -27,7 +27,7 @@ package socbridge_driver_tb_pkg is
     curr_inst : controller_to_socbridge_driver_t;
     curr_state : translator_state_t;
     is_first_word : std_logic;
-  end record translator_state_rec_t; 
+  end record translator_state_rec_t;
 
   type ext_protocol_t is record
     data   : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
@@ -36,10 +36,12 @@ package socbridge_driver_tb_pkg is
   end record ext_protocol_t;
 
   type state_rec_t is record
-    curr_state: state_t;
+    curr_rx_transaction : transaction_t;
+    curr_tx_transaction : transaction_t;
+    curr_rx_state: rx_state_t;
+    curr_tx_state: tx_state_t;
     ext_to_socbridge_driver_reg, socbridge_driver_to_ext_reg : ext_protocol_t; 
-    write_stage, read_stage : NATURAL;
-    curr_cmd : command_t;
+    tx_stage, rx_stage : NATURAL;
     curr_cmd_size: integer;
     curr_addr : std_logic_vector(31 downto 0);
   end record state_rec_t;
@@ -50,7 +52,7 @@ package socbridge_driver_tb_pkg is
   input: ext_protocol_t
   ) return socbridge_driver_to_ext_t;
   function to_string ( a: std_logic_vector) return string;
-  pure function get_cmd_bits(command : command_t) return std_logic_vector;
+  pure function get_header_bits(command : transaction_t) return std_logic_vector;
   pure function get_size_bits(size : command_size_t) return std_logic_vector;
   pure function get_size_bits_sim(size : command_size_t) return std_logic_vector;
   --- DEBUG GLOBAL SIGNALS ---
@@ -58,7 +60,8 @@ package socbridge_driver_tb_pkg is
   signal G_next_parity_out : std_logic;
   signal G_ext_to_socbridge_driver_rec : ext_protocol_t;
   signal G_socbridge_driver_to_ext_data_cmd : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
-  signal G_next_state : state_t;
+  signal G_next_rx_state : rx_state_t;
+  signal G_next_tx_state : tx_state_t;
   signal G_curr_command : command_t;
   signal G_curr_command_bits : std_logic_vector(4 downto 0);
   signal G_curr_response : response_t;
@@ -105,18 +108,25 @@ package body socbridge_driver_tb_pkg is
     val.control(0) := input.parity;
     return val;
   end function;
-  pure function get_cmd_bits(command : command_t) 
+
+  pure function get_header_bits(transaction : transaction_t) 
     return std_logic_vector is
   variable val : std_logic_vector(4 downto 0);
   begin
-    with command select
-      val := "00000" when NO_OP,
-             "10000" when WRITE_ADD,
-             "10100" when WRITE,
-             "11000" when READ_ADD,
-             "11100" when READ,
-             "01001" when P_ERR,      
-             "11111" when others;   
+    val := "11111";
+    if transaction = NO_OP then
+    val := "00000";
+    elsif transaction = WRITE_ADD then
+    val := "10000";
+    elsif transaction = WRITE then
+    val := "10100";
+    elsif transaction = READ_ADD then
+    val := "11000";
+    elsif transaction = READ then
+    val := "11100";
+    elsif transaction = P_ERR then
+    val := "01001";
+    end if;
     return val;
   end function;
   

src/vhdl_ls.toml

@@ -3,15 +3,28 @@ standard = "1993"
 # File names are either absolute or relative to the parent folder of the vhdl_ls.toml file
 [libraries]
 ganimede.files = [
-    'ganimede/io_type_pkg.vhd'
+    'ganimede/io_type_pkg.vhd',
+    'ganimede/ganimede.vhd'
 ]
-socbridge.files = [
+gan_socbridge.files = [
     'socbridge/*.vhd'
 ]
 
 controller.files = [
     'controller/*.vhd',
 ]
+manager.files = [
+    'manager/*.vhd',
+]
+grlib.files = [
+   'grlib-com-nx-2024.4-b4295/lib/grlib/**/*.vhd',
+]
+techmap.files = [
+   'grlib-com-nx-2024.4-b4295/lib/techmap/gencomp/**/*.vhd',
+]
+gaisler.files = [
+   'grlib-com-nx-2024.4-b4295/lib/gaisler/**/*.vhd',
+]
 
 [lint]
 unused = 'error' # Upgrade the 'unused' diagnostic to the 'error' severity