fixed bugs arising from rebase

Reviewed-on: #19

src/dummy_ip/dummy_ip.vhd

@@ -3,44 +3,37 @@ use IEEE.std_logic_1164.all;
 use IEEE.NUMERIC_STD.all;
 
 entity dummy_ip is
-  generic (
-    data_width : natural := 8
-  );
   port (
     clk, rst : in std_logic;
     ready_in, valid_in : in std_logic;
     ready_out, valid_out : out std_logic;
-    data_in : in std_logic_vector(data_width - 1 downto 0);
-    data_out : out std_logic_vector(data_width - 1 downto 0)
+    data_in : in std_logic_vector(8 - 1 downto 0);
+    data_out : out std_logic_vector(8 - 1 downto 0)
   );
 end entity dummy_ip;
 
 architecture rtl of dummy_ip is
-  signal incremented_in : std_logic_vector(data_width - 1 downto 0);
-  signal valid_out_signal : std_logic;
+  signal incremented_in : std_logic_vector(8 - 1 downto 0);
 begin
  
-valid_out <= valid_out_signal;
-data_out  <= incremented_in;  
+comb_proc: process(ready_in, valid_in, data_in, incremented_in)
+begin
+  ready_out <= ready_in;
+end process;
 
-seq_proc: process(clk, data_in, ready_in, valid_in)
+seq_proc: process(clk,rst)
 begin
   if rst = '1' then
-    incremented_in <= (others => '0');
-    valid_out_signal <= '0';
-    ready_out <= '1';
-  else
-    if rising_edge(clk) then
-      if valid_in = '1' then 
-        valid_out_signal <= '1';
-        ready_out <= '0';
-      elsif valid_out_signal = '1' and ready_in = '1' then
-        valid_out_signal <= '0';
-        ready_out <= '1';
-      end if; 
-    elsif falling_edge(clk)then
-      incremented_in <= std_logic_vector(unsigned(data_in) + 1);    
-    end if;
+    valid_out <= '0';
+    data_out <= (others => '0');
+  elsif rising_edge(clk) then
+    if valid_in = '1' and ready_in = '1' then 
+      valid_out <= '1';
+      data_out <= std_logic_vector(unsigned(data_in) + 1);    
+    else
+      valid_out <= '0';
+    end if; 
+  elsif falling_edge(clk) then
   end if;
 end process seq_proc;
   

src/fifo_buffer/fifo_buffer.vhd

@@ -35,21 +35,6 @@ architecture rtl of fifo_buffer is
   signal inverted_in_clock : std_logic;
   signal customout       : std_logic_vector(0 downto 0); -- techmap needs customout and it is does not have a default value for some reason
 begin
- 
--- DECLARATION OF NX_SYNCRAM
---entity nx_syncram_be is
---  generic ( abits : integer    := 6;
---            dbits : integer    := 8
---            );
---  port (
---    clk     : in  std_ulogic;
---    address : in  std_logic_vector  (abits -1  downto 0);
---    datain  : in  std_logic_vector  (dbits -1  downto 0);
---    dataout : out std_logic_vector  (dbits -1  downto 0);
---    enable  : in  std_logic_vector  (dbits/8-1 downto 0);
---    write   : in  std_logic_vector  (dbits/8-1 downto 0)
---    );
---end;
 
   techmap_ram_inst : entity techmap.syncram_2p
   generic map(tech => tech, 
@@ -101,10 +86,12 @@ begin
       read_pointer <= (others => '0');
       write_pointer <= (others => '0');
   else
-    if rising_edge(in_clk) and valid_in = '1' and buffer_full = '0' then
-      write_pointer <= std_logic_vector(unsigned(write_pointer) + 1);
+    if rising_edge(in_clk) then
+      if valid_in = '1' and buffer_full = '0'then
+        write_pointer <= std_logic_vector(unsigned(write_pointer) + 1);
+      end if;
     end if;
-    if falling_edge(out_clk) then
+    if rising_edge(out_clk) then
       if ready_in = '1' and buffer_empty = '0' then
         read_pointer <= std_logic_vector(unsigned(read_pointer) + 1);
         valid_out <= '1';

src/fifo_buffer/fifo_deserializer.vhd

@@ -6,7 +6,8 @@ use ieee.numeric_std.all;
 entity fifo_deserializer is
   generic (
     output_width : natural := 8;
-    input_width  : natural := 8
+    input_width  : natural := 8;
+    endianess    : integer := 0  -- 0: little endian, 1: big endian
   );
   port (
     rst, clk : in std_logic;
@@ -21,26 +22,24 @@ end entity fifo_deserializer;
 
 architecture rtl of fifo_deserializer is
 
-constant out_over_in : natural := output_width / input_width;
+constant out_over_in : natural := output_width / input_width - 1;
 type state_t is record
   count : integer;
   data : std_logic_vector(output_width - 1 downto 0);
+  full_word : std_logic;
+  prev_ready : std_logic;
 end record state_t;
 signal st : state_t;
 begin
 
 comb_proc: process(rst,clk,valid_in,ready_in,data_in,st)
 begin
-  if st.count = out_over_in then
+  if st.full_word = '1' and ready_in = '1' then
     valid_out <= '1';
   else 
     valid_out <= '0';
   end if;
-  if not (st.count = out_over_in) and ready_in = '1' then
-    ready_out <= '1';
-  else 
-    ready_out <= '0';
-  end if;
+  ready_out <= ready_in;
   data_out <= st.data;
 end process comb_proc; 
 
@@ -49,12 +48,25 @@ begin
   if rst = '1' then
     st.count <= 0;
     st.data <= (others => '0');
+    st.full_word <= '0';
+    st.prev_ready <= '0';
   elsif (rising_edge(clk)) then
-    if st.count = out_over_in then
+    st.prev_ready <= ready_in;
+    if valid_in = '1' and st.prev_ready = '1' then
+      if endianess = 0 then
+        st.data((out_over_in + 1 - st.count) * input_width  - 1 downto (out_over_in - st.count) * input_width) <= data_in;
+      else
+        st.data((st.count + 1) * input_width - 1 downto st.count * input_width) <= data_in;
+      end if;
+    end if;
+    if st.full_word = '1' and ready_in = '1' then
+      st.full_word <= '0';
+    end if;
+    if st.count = out_over_in and valid_in = '1' then
+      st.full_word <= '1';
       st.count <= 0;
-    elsif valid_in = '1' and ready_in = '1' then
+    elsif valid_in = '1' then
       st.count <= st.count + 1;
-      st.data((st.count + 1) * input_width - 1 downto st.count * input_width) <= data_in;
     end if;
   end if;
 end process seq_proc;

src/fifo_buffer/fifo_serializer.vhd

@@ -7,7 +7,7 @@ entity fifo_serializer is
   generic (
     output_width : natural := 8;
     input_width  : natural := 8;
-    endianess    : integer := 1
+    endianess    : integer := 0 -- 0: little endian, 1: big endian
   );
   port (
     rst, clk : in std_logic;
@@ -41,9 +41,9 @@ begin
   valid_out <= st.valid;
   if st.count <= in_over_out and st.valid = '1' then
     if endianess = 0 then
-      data_out <= st.data((st.count + 1) * output_width - 1 downto st.count * output_width);
-    else
       data_out <= st.data((input_width - st.count * output_width) - 1 downto input_width - (st.count + 1) * output_width);
+    else
+      data_out <= st.data((st.count + 1) * output_width - 1 downto st.count * output_width);
     end if;
   else
     data_out <= (others => '0');

src/ganimede/ganimede.vhd

@@ -10,6 +10,9 @@ use gan_manager.management_types.all;
 library gan_buffer;
 
 entity ganimede_toplevel is
+  generic (
+    tech : integer := 0
+          );
   port (
     clk               : in  std_logic;
     rst               : in  std_logic;
@@ -31,7 +34,9 @@ architecture rtl of ganimede_toplevel is
   signal buffer_to_socbridge_driver : fifo_interface_t;
   signal ip_to_socbridge_driver : ip_to_socbridge_driver_t;
   signal socbridge_clk : std_logic;
+  signal ganimede_to_ip_reset : std_logic;
 
+  constant buf_size :integer := 2*1024;
   --signal gan_socbridge_WE_in : std_logic;
   --signal gan_socbridge_WE_out : std_logic;
   --signal gan_socbridge_is_full_in : std_logic;
@@ -41,9 +46,17 @@ begin
   --- INTERNAL CONNECTIONS ---
   ip_to_socbridge_driver.fifo <= buffer_to_socbridge_driver;
   ip_to_socbridge_driver.flush <= ip_to_ganimede.socbridge.flush;
+  ip_to_socbridge_driver.read_fifo.data <= (others => '0');
+  ip_to_socbridge_driver.read_fifo.valid <= '0';
+  ip_to_socbridge_driver.read_fifo.ready <= '0';
+  ganimede_to_ip.socbridge.used_slots <= 0;
+  ganimede_to_ip_reset <= rst or ip_to_ganimede.socbridge.flush;
 
   --- DRIVER INSTANTIATION ---
   socbridge_driver_inst: entity gan_socbridge.socbridge_driver
+    generic map(
+      BUFFER_SIZE => buf_size
+    )
     port map(
       clk                            => clk,
       socbridge_clk                  => socbridge_clk,
@@ -80,25 +93,26 @@ begin
 
   fifo_buffer_to_ip_inst : entity gan_buffer.fifo_buffer
     generic map (
-      buffer_size => 1024
-      --tech => 60
+      buffer_size => buf_size,
+      tech => tech
     )
     port map(
       in_clk => socbridge_clk,
       out_clk => clk,
-      rst => rst,
+      rst => ganimede_to_ip_reset,
       ready_in => ip_to_ganimede.socbridge.fifo.ready,
       ready_out => buffer_to_socbridge_driver.ready,
       valid_in => socbridge_driver_to_buffer.valid,
       valid_out => ganimede_to_ip.socbridge.valid,
       data_in => socbridge_driver_to_buffer.data,
-      data_out => ganimede_to_ip.socbridge.data
+      data_out => ganimede_to_ip.socbridge.data,
+      used_slots => ip_to_socbridge_driver.read_fifo.used_slots
     );
 
   fifo_buffer_from_ip_inst : entity gan_buffer.fifo_buffer
     generic map (
-      buffer_size => 1024
---      tech => 60
+      buffer_size => buf_size,
+      tech => tech
     )
     port map(
       in_clk => clk, 

src/ganimede/io_type_pkg.vhd

@@ -73,6 +73,7 @@ package io_types is
 
   type ip_to_socbridge_driver_t is record
     fifo: fifo_interface_t;
+    read_fifo: fifo_interface_t;
     flush: std_logic;
   end record ip_to_socbridge_driver_t;
 

src/manager/management_unit.vhd

@@ -53,20 +53,22 @@ begin
   manager_to_socbridge_driver.ready <= '1';
   manager_to_socbridge_driver.data <= pack(manager_state.memory(local_word_address));
   manager_to_socbridge_driver.valid <= '1';
-  word_address  <= local_word_address;
+  word_address <= local_word_address;
   manager_to_controller.cmd <= cmd;
 end process comb_proc;
 
 -- tre sorters sätt att avsluta en skrivning:
 -- timeout om vi villha det
--- en lastbit genooom axi interface
+-- en lastbit genom axi interface
 -- vi har fått all data vi begärde.
 
 seq_proc: process(clk)
 begin
   if rising_edge(clk) then
     if rst = '1' then
-      manager_state <= manager_state_reset_val;
+      manager_state.data_out <= manager_word_reset_val;
+      manager_state.memory(0).reserved(0) <= '0';
+      manager_state.memory(1).reserved(0) <= '0';
     else
       -- Write data from SoCBridge driver to address
       if socbridge_driver_to_manager.valid = '1' then
@@ -78,20 +80,20 @@ begin
       -- Is the controller done executing an instruction
       else
         if controller_to_manager.done_reading = '1' then
-          manager_state.memory(0) <= manager_word_reset_val;
+          manager_state.memory(0).reserved(0) <= '0';
         end if;
         if controller_to_manager.done_writing = '1' then
-          manager_state.memory(1) <= manager_word_reset_val;
+          manager_state.memory(1).reserved(0) <= '0';
         end if;
       end if;
       -- Is there a read instruction in memory
-      if pack(read_address) /= empty_word and controller_to_manager.ready = '1' and controller_to_manager.done_reading = '0' then
+      if read_address.reserved(0) = '1' and controller_to_manager.ready = '1' and controller_to_manager.done_reading = '0' then
         manager_to_controller.address <= read_address.address & "0000000000";
         manager_to_controller.driver_id <= "1"; -- Only supprts one driver at present
         manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10;
         cmd <= "10";
       -- Is there a write instruction in memory
-      elsif pack(write_address) /= empty_word and controller_to_manager.ready = '1' and controller_to_manager.done_writing = '0'then
+      elsif write_address.reserved(0) = '1' and controller_to_manager.ready = '1' and controller_to_manager.done_writing = '0'then
         manager_to_controller.address <= write_address.address & "0000000000";
         manager_to_controller.driver_id <= "1"; -- Only supports one driver at present
         manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10;

src/manager/management_unit_pkg.vhd

@@ -16,7 +16,8 @@ package management_types is
     reserved: std_logic_vector(WORD_SIZE - 1 - (22 + 4 + 3) downto 0);
   end record manager_word_t;
   constant empty_word : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0');
-  constant mem_words : natural := 64;
+  constant mem_words : natural := 2;
+  constant min_bits_to_determine_address : natural := natural(CEIL(LOG2(real(mem_words))));
   constant address_mask : std_logic_vector(WORD_SIZE - 1 downto 0) := std_logic_vector(to_unsigned(mem_words - 1, 32));
   type memory_t is array (0 to mem_words - 1) of manager_word_t;
 

src/socbridge/socbridge_driver.vhd

@@ -13,7 +13,8 @@ use grlib.stdlib.all;
 
 entity socbridge_driver is
   generic(
-    MAX_PKT_SIZE : integer range 1 to 128 := 32
+    MAX_PKT_SIZE : integer range 1 to 128 := 8;
+    BUFFER_SIZE : integer
          );
   port(
     clk                            : in std_logic;
@@ -31,43 +32,43 @@ entity socbridge_driver is
 end entity socbridge_driver;
 
 architecture rtl of socbridge_driver is
-  
+  type slice is array(0 to 3) of natural;
+  constant next_slice_32_8_upper : slice := (31, 7, 15, 23);
+  constant next_slice_32_8_lower : slice := (24, 0, 8, 16);
+
   signal next_parity_out                           : std_logic;
-  signal ext_to_socbridge_driver_rec               : ext_protocol_t;
-  signal next_data_out : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
-  signal next_rx_transaction                   : transaction_t;
-  signal next_tx_transaction                   : transaction_t;
-  signal next_tx_data_size, next_rx_data_size          : integer;
+  signal next_data_out                             : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
+  signal next_rx_transaction                       : transaction_t;
+  signal next_tx_transaction                       : transaction_t;
+  signal next_tx_data_size, next_rx_data_size      : natural;
   signal next_rx_state                             : rx_state_t;
   signal next_tx_state                             : tx_state_t;
   signal st                                        : state_rec_t;
-  signal valid_out                                 : std_logic;
   --- TRANSLATOR ---
   signal trans_st : translator_state_t;
   signal trans_read_next_state : ctrl_inst_state_t;
   signal trans_write_next_state : ctrl_inst_state_t;
   --- FSM COMMUNICATION ---
-  signal tx_sent_response, rx_received_response    : std_logic;
   --- MANAGEMENT COMMUNICATION ---
 begin
-  ext_to_socbridge_driver_rec.data <= ext_to_socbridge_driver.payload;
-  ext_to_socbridge_driver_rec.clk <= ext_to_socbridge_driver.control(1);
-  ext_to_socbridge_driver_rec.parity <= ext_to_socbridge_driver.control(0);
-  socbridge_clk <= ext_to_socbridge_driver_rec.clk;
 
   comb_proc: process(ext_to_socbridge_driver, ip_to_socbridge_driver, 
-                     st, controller_to_socbridge_driver, trans_st,
-                     tx_sent_response, rx_received_response,
-                     valid_out)
+                     controller_to_socbridge_driver, st, trans_st)
     variable curr_response_bits : std_logic_vector(4 downto 0);
     variable local_next_rx_transaction : transaction_t;
     variable local_next_tx_transaction : transaction_t;
     variable local_next_data_out :  std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
+    variable ext_to_socbridge_driver_rec : ext_protocol_t;
   begin
     -- DEFAULT VALUES
     -- Helpful Bindings --
-    next_rx_data_size <= 2 ** to_integer(unsigned(ext_to_socbridge_driver.payload(2 downto 0)));
-    curr_response_bits := ext_to_socbridge_driver.payload(7 downto 3); 
+    ext_to_socbridge_driver_rec.data := ext_to_socbridge_driver.payload;
+    ext_to_socbridge_driver_rec.clk := ext_to_socbridge_driver.control(1);
+    ext_to_socbridge_driver_rec.parity := ext_to_socbridge_driver.control(0);
+    socbridge_clk <= ext_to_socbridge_driver_rec.clk;
+    socbridge_driver_to_ip.used_slots <= 0;
+    next_rx_data_size <= 2 ** to_integer(unsigned(ext_to_socbridge_driver_rec.data(2 downto 0)));
+    curr_response_bits := ext_to_socbridge_driver_rec.data(7 downto 3); 
       -- Set helper var to current transaction seen at the input.
     local_next_rx_transaction := NO_OP;
     if curr_response_bits = "10000" then 
@@ -89,12 +90,12 @@ begin
     socbridge_driver_to_ext.payload <= st.socbridge_driver_to_ext_reg.data;
     socbridge_driver_to_ext.control(0) <= st.socbridge_driver_to_ext_reg.parity;
     socbridge_driver_to_ext.control(1) <= st.socbridge_driver_to_ext_reg.clk;
-    if trans_st.read.curr_state = IDLE then
+    if trans_st.read.state = IDLE then
       socbridge_driver_to_controller.is_reading <= '0';
     else 
       socbridge_driver_to_controller.is_reading <= '1';
     end if;
-    if trans_st.write.curr_state = IDLE then
+    if trans_st.write.state = IDLE then
       socbridge_driver_to_controller.is_writing <= '0';
     else 
       socbridge_driver_to_controller.is_writing <= '1';
@@ -102,23 +103,27 @@ begin
 
     --- Next State Assignments --- 
       --- ### TX NEXT STATE ASSIGNMENTS ### ---
-    case st.curr_tx_state is
+    case st.tx_state is
       when IDLE =>
-        if local_next_tx_transaction /= NO_OP then
+        if (local_next_tx_transaction = WRITE or local_next_tx_transaction = WRITE_ADD) and not st.write_in_flight then
+          next_tx_state <= TX_HEADER;
+        elsif (local_next_tx_transaction = READ or local_next_tx_transaction = READ_ADD) and not st.read_in_flight then
+          next_tx_state <= TX_HEADER;
+        elsif local_next_tx_transaction = READ_RESPONSE or local_next_tx_transaction = WRITE_ACK then
           next_tx_state <= TX_HEADER;
         else 
           next_tx_state <= IDLE;
         end if;
       when TX_HEADER =>
         -- Commands
-        if st.curr_tx_transaction = WRITE_ADD or st.curr_tx_transaction = READ_ADD then
+        if st.tx_transaction = WRITE_ADD or st.tx_transaction = READ_ADD then
           next_tx_state <= ADDR1;
-        elsif st.curr_tx_transaction = WRITE then 
+        elsif st.tx_transaction = WRITE then 
           next_tx_state <= TX_W_BODY;
-        elsif st.curr_tx_transaction = READ then
-          next_tx_state <= TX_AWAIT;
+        elsif st.tx_transaction = READ then
+          next_tx_state <= IDLE;
         -- Responses
-        elsif st.curr_tx_transaction = READ_RESPONSE then
+        elsif st.tx_transaction = READ_RESPONSE then
           next_tx_state <= TX_R_BODY;
         else
           next_tx_state <= IDLE;
@@ -136,33 +141,22 @@ begin
       when ADDR3 =>
         next_tx_state <= ADDR4;
       when ADDR4 => 
-        if st.curr_tx_transaction = READ_ADD then 
-          next_tx_state <= TX_AWAIT;
-        elsif st.curr_tx_transaction = WRITE_ADD then 
+        if st.tx_transaction = READ_ADD then 
+          next_tx_state <= IDLE;
+        elsif st.tx_transaction = WRITE_ADD then 
           next_tx_state <= TX_W_BODY;
         else 
           next_tx_state <= IDLE;
         end if;
       when TX_W_BODY =>
         if st.tx_stage <= 1 then
-          next_tx_state <= TX_AWAIT;
+          next_tx_state <= IDLE;
         else 
           next_tx_state <= TX_W_BODY;
         end if;
-      when TX_AWAIT => 
-        -- Wait for RX FSM to get a response
-        if (st.curr_tx_transaction = WRITE_ADD or st.curr_tx_transaction = WRITE)
-        and st.curr_rx_transaction = WRITE_ACK then
-          next_tx_state <= IDLE;
-        elsif (st.curr_tx_transaction = READ_ADD or st.curr_tx_transaction = READ)
-        and st.curr_rx_transaction = READ_RESPONSE and (st.rx_stage = 1 or next_tx_transaction = WRITE or next_tx_transaction = WRITE_ADD) then
-          next_tx_state <= IDLE;
-        else 
-          next_tx_state <= TX_AWAIT;
-        end if;
     end case;
   --- Next State Assignment Of RX FSM --- 
-    case st.curr_rx_state is
+    case st.rx_state is
       when IDLE => 
         if local_next_rx_transaction /= NO_OP then 
           next_rx_state <= RX_HEADER;
@@ -171,21 +165,27 @@ begin
         end if;
       when RX_HEADER =>
         -- Commands
-        if st.curr_rx_transaction = WRITE_ADD or st.curr_rx_transaction = READ_ADD then
+        if st.rx_transaction = WRITE_ADD or st.rx_transaction = READ_ADD then
           next_rx_state <= ADDR1;
-        elsif st.curr_rx_transaction = WRITE then 
+        elsif st.rx_transaction = WRITE then 
           next_rx_state <= RX_W_BODY;
-        elsif st.curr_rx_transaction = READ then
+        elsif st.rx_transaction = READ then
           next_rx_state <= RX_AWAIT;
         -- Responses
-        elsif st.curr_rx_transaction = READ_RESPONSE then
+        elsif st.rx_transaction = READ_RESPONSE then
           next_rx_state <= RX_R_BODY;
-        else 
+        elsif local_next_rx_transaction /= NO_OP then
+          next_rx_state <= RX_HEADER;
+        else
           next_rx_state <= IDLE;
         end if;
       when RX_R_BODY =>
         if st.rx_stage <= 1 then
-          next_rx_state <= IDLE;
+          if local_next_rx_transaction /= NO_OP then
+            next_rx_state <= RX_HEADER;
+          else
+            next_rx_state <= IDLE;
+          end if;
         else
           next_rx_state <= RX_R_BODY;
         end if;
@@ -196,9 +196,9 @@ begin
       when ADDR3 =>
         next_rx_state <= ADDR4;
       when ADDR4 =>
-        if st.curr_rx_transaction = READ_ADD then 
+        if st.rx_transaction = READ_ADD then 
           next_rx_state <= RX_AWAIT;
-        elsif st.curr_rx_transaction = WRITE_ADD then
+        elsif st.rx_transaction = WRITE_ADD then
           next_rx_state <= RX_W_BODY;
         else
           next_rx_state <= IDLE; -- Potentially superfluous safety
@@ -211,11 +211,11 @@ begin
         end if;
       when RX_AWAIT =>
         -- Wait for TX FSM to send a response
-        if (st.curr_rx_transaction = WRITE_ADD or st.curr_rx_transaction = WRITE)
-        and st.curr_tx_transaction = WRITE_ACK then
+        if (st.rx_transaction = WRITE_ADD or st.rx_transaction = WRITE)
+        and st.tx_transaction = WRITE_ACK then
           next_rx_state <= IDLE;
-        elsif (st.curr_rx_transaction = READ_ADD or st.curr_rx_transaction = READ)
-        and st.curr_tx_transaction = READ_RESPONSE and st.tx_stage = 1 then
+        elsif (st.rx_transaction = READ_ADD or st.rx_transaction = READ)
+        and st.tx_transaction = READ_RESPONSE and st.tx_stage = 1 then
           next_rx_state <= IDLE;
         else 
           next_rx_state <= RX_AWAIT;
@@ -227,17 +227,22 @@ begin
     local_next_data_out := (others => '0');
     socbridge_driver_to_ip.ready <= '0';
     --- ### TX_STATE BASED OUTPUT ### ---
-    case st.curr_tx_state is
+    case st.tx_state is
       when IDLE => 
       when TX_HEADER =>
-        if st.curr_tx_transaction = WRITE_ACK or st.curr_tx_transaction = READ_RESPONSE then
-          local_next_data_out := get_header_bits(st.curr_tx_transaction, st.curr_rx_transaction) & get_size_bits(st.rx_data_size);
+        if st.tx_transaction = WRITE_ACK or st.tx_transaction = READ_RESPONSE then
+          local_next_data_out := get_header_bits(st.tx_transaction, st.rx_transaction) & get_size_bits(st.rx_data_size);
         else 
-          local_next_data_out := get_header_bits(st.curr_tx_transaction, st.curr_rx_transaction) & get_size_bits(st.tx_data_size);
+          local_next_data_out := get_header_bits(st.tx_transaction, st.rx_transaction) & get_size_bits(st.tx_data_size);
+        end if;
+        if st.tx_transaction = WRITE then
+          socbridge_driver_to_ip.ready <= '1';
         end if;
       when TX_W_BODY =>
-        if st.tx_stage > 0 then
+        if st.tx_stage > 1 then
           socbridge_driver_to_ip.ready <= '1';
+        end if;
+        if st.tx_stage > 0 then
           if ip_to_socbridge_driver.fifo.valid = '1' then
             local_next_data_out := ip_to_socbridge_driver.fifo.data;
           else
@@ -246,54 +251,48 @@ begin
         end if;
       when TX_R_BODY =>
         if st.tx_stage > 0 then
-          local_next_data_out := st.curr_read_data((((st.tx_stage - 1) mod 4) + 1) * 8 - 1 downto ((((st.tx_stage - 1) mod 4) + 1) - 1) * 8);
+          local_next_data_out := st.manager_data(next_slice_32_8_upper(st.tx_stage mod 4) downto next_slice_32_8_lower(st.tx_stage mod 4));
         end if;
-      when TX_AWAIT =>
       when ADDR1 =>
-        local_next_data_out := st.curr_tx_addr(31 downto 24);
+        local_next_data_out := st.tx_addr(31 downto 24);
       when ADDR2 =>
-        local_next_data_out := st.curr_tx_addr(23 downto 16);
+        local_next_data_out := st.tx_addr(23 downto 16);
       when ADDR3 =>
-        local_next_data_out := st.curr_tx_addr(15 downto 8);
+        local_next_data_out := st.tx_addr(15 downto 8);
       when ADDR4 =>
-        local_next_data_out := st.curr_tx_addr(7 downto 0);
+        local_next_data_out := st.tx_addr(7 downto 0);
+        if st.tx_transaction = WRITE_ADD then
+          socbridge_driver_to_ip.ready <= '1';
+        end if;
     end case;
     --- ### RX_STATE BASED OUTPUT ### ---
     socbridge_driver_to_manager.valid <= '0';
-    socbridge_driver_to_manager.address <= (others => '0');
-    socbridge_driver_to_manager.data <= (others => '0');
-    case st.curr_rx_state is
-      when IDLE => 
-      when RX_HEADER =>
+    socbridge_driver_to_manager.data <= st.manager_data;
+    socbridge_driver_to_manager.address <= st.manager_addr;
+    socbridge_driver_to_ip.valid <= '0';
+    socbridge_driver_to_ip.data <= st.ext_to_socbridge_driver_reg.data;
+    case st.rx_state is
       when RX_W_BODY =>
         if st.rx_stage  mod 4 = 0 and st.rx_stage /= st.rx_data_size then
-          socbridge_driver_to_manager.data <= st.curr_write_data;
-          socbridge_driver_to_manager.address <= st.curr_rx_write_addr;
           socbridge_driver_to_manager.valid <= '1';
         end if;
       when RX_R_BODY =>
+        socbridge_driver_to_ip.valid <= '1';
       when RX_AWAIT =>
-        if st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then
-          socbridge_driver_to_manager.data <= st.curr_write_data;
-          socbridge_driver_to_manager.address <= st.curr_rx_write_addr;
+        if st.rx_transaction = WRITE or st.rx_transaction = WRITE_ADD then
           socbridge_driver_to_manager.valid <= '1';
-        else 
-          socbridge_driver_to_manager.address <= st.curr_rx_read_addr;
         end if;
-      when ADDR1 =>
-      when ADDR2 =>
-      when ADDR3 =>
-      when ADDR4 =>
+      when others =>
     end case;
     next_parity_out <= calc_parity(local_next_data_out);
     --- TRANSLATOR ---
       --- Next state assignment
-    case trans_st.write.curr_state is
+    case trans_st.write.state is
       when IDLE =>
-        if st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD
-        or st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then
+        if st.rx_transaction = READ or st.rx_transaction = READ_ADD
+        or st.rx_transaction = WRITE or st.rx_transaction = WRITE_ADD then
           trans_write_next_state <= IDLE;
-        elsif trans_st.write.curr_inst.request = '1' and (ip_to_socbridge_driver.fifo.used_slots >= MAX_PKT_SIZE 
+        elsif trans_st.write.inst.request = '1' and (ip_to_socbridge_driver.fifo.used_slots >= MAX_PKT_SIZE 
           or ip_to_socbridge_driver.flush = '1') then
           trans_write_next_state <= SEND;
         else 
@@ -301,7 +300,7 @@ begin
         end if;
       -- Wait for driver to go idle and send next instruction. Then enter AWAIT
       when SEND =>
-        if st.curr_tx_transaction = WRITE or st.curr_tx_transaction = WRITE_ADD then
+        if st.tx_transaction = WRITE or st.tx_transaction = WRITE_ADD then
           trans_write_next_state <= SEND_ACCEPTED;
         else 
           trans_write_next_state <= SEND;
@@ -311,34 +310,34 @@ begin
         trans_write_next_state <= AWAIT;
       -- Wait for driver to finish current instruction, then reenter SEND
       when AWAIT =>
-        if trans_st.write.curr_inst.seq_mem_access_count <= MAX_PKT_SIZE and st.curr_tx_state = IDLE then
+        if trans_st.write.inst.access_count <= MAX_PKT_SIZE and not st.write_in_flight then
           trans_write_next_state <= IDLE;
         elsif ip_to_socbridge_driver.fifo.used_slots = 0 and ip_to_socbridge_driver.flush = '1'
-              and st.curr_tx_state = IDLE then
+              and not st.write_in_flight then
           trans_write_next_state <= IDLE;
-        elsif st.curr_tx_state = IDLE and (ip_to_socbridge_driver.fifo.used_slots >= MAX_PKT_SIZE
+        elsif not st.write_in_flight and (ip_to_socbridge_driver.fifo.used_slots >= MAX_PKT_SIZE
           or ip_to_socbridge_driver.flush = '1') then
           trans_write_next_state <= SEND;
         else 
           trans_write_next_state <= AWAIT;
         end if;
     end case;
-    case trans_st.read.curr_state is
+    case trans_st.read.state is
       when IDLE =>
         if next_rx_transaction = READ or next_rx_transaction = READ_ADD
         or next_rx_transaction = WRITE or next_rx_transaction = WRITE_ADD then
           trans_read_next_state <= IDLE;
-        elsif st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD
-        or st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then
+        elsif st.rx_transaction = READ or st.rx_transaction = READ_ADD
+        or st.rx_transaction = WRITE or st.rx_transaction = WRITE_ADD then
           trans_read_next_state <= IDLE;
-        elsif trans_st.read.curr_inst.request = '1' then
+        elsif trans_st.read.inst.request = '1' and BUFFER_SIZE - ip_to_socbridge_driver.read_fifo.used_slots > 2*MAX_PKT_SIZE then
           trans_read_next_state <= SEND;
         else 
           trans_read_next_state <= IDLE;
         end if;
       -- Wait for driver to go idle and send next instruction. Then enter AWAIT
       when SEND =>
-        if st.curr_tx_transaction = READ or st.curr_tx_transaction = READ_ADD then
+        if st.tx_transaction = READ or st.tx_transaction = READ_ADD then
           trans_read_next_state <= SEND_ACCEPTED;
         else 
           trans_read_next_state <= SEND;
@@ -348,11 +347,11 @@ begin
         trans_read_next_state <= AWAIT;
       -- Wait for driver to finish current instruction, then reenter SEND
       when AWAIT =>
-        if trans_st.read.curr_inst.seq_mem_access_count <= MAX_PKT_SIZE and st.curr_tx_state = IDLE then
+        if trans_st.read.inst.access_count <= MAX_PKT_SIZE and not st.read_in_flight then
           trans_read_next_state <= IDLE;
-        elsif ip_to_socbridge_driver.flush = '1'and st.curr_tx_state = IDLE then
+        elsif ip_to_socbridge_driver.flush = '1'and not st.read_in_flight then
           trans_read_next_state <= IDLE;
-        elsif st.curr_tx_state = IDLE then
+        elsif not st.read_in_flight and BUFFER_SIZE - ip_to_socbridge_driver.read_fifo.used_slots > 2*MAX_PKT_SIZE then
           trans_read_next_state <= SEND;
         else 
           trans_read_next_state <= AWAIT;
@@ -362,36 +361,37 @@ begin
     --- NEXT TX TRANSACTION ---
     local_next_tx_transaction := NO_OP;
     next_tx_data_size <= 0;
-    if trans_st.read.curr_state = IDLE and trans_st.write.curr_state = IDLE and st.curr_rx_state = RX_AWAIT then
-      if (st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD) and manager_to_socbridge_driver.ready = '1' then
+    if trans_st.read.state = IDLE and trans_st.write.state = IDLE and st.rx_state = RX_AWAIT then
+      if (st.rx_transaction = WRITE or st.rx_transaction = WRITE_ADD) and manager_to_socbridge_driver.ready = '1' then
         local_next_tx_transaction := WRITE_ACK;
-      elsif (st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD) and manager_to_socbridge_driver.valid = '1' then
+      elsif (st.rx_transaction = READ or st.rx_transaction = READ_ADD) and manager_to_socbridge_driver.valid = '1' then
         next_tx_data_size <= st.rx_data_size;
         local_next_tx_transaction := READ_RESPONSE;
       end if;
-    elsif trans_st.read.curr_state = SEND then
+    elsif trans_st.read.state = SEND 
+    and not ((st.last_sent_transaction = READ or st.last_sent_transaction = READ_ADD) and trans_st.write.state = SEND) then
       if trans_st.read.is_first_word = '1' then 
         local_next_tx_transaction := READ_ADD;
       else 
         local_next_tx_transaction := READ;
       end if;
-      if trans_st.read.curr_inst.seq_mem_access_count > MAX_PKT_SIZE then
+      if trans_st.read.inst.access_count > MAX_PKT_SIZE then
         next_tx_data_size <= MAX_PKT_SIZE;
-      elsif trans_st.read.curr_inst.seq_mem_access_count > 0 then
-        next_tx_data_size <= trans_st.read.curr_inst.seq_mem_access_count;
+      elsif trans_st.read.inst.access_count > 0 then
+        next_tx_data_size <= trans_st.read.inst.access_count;
       else 
         next_tx_data_size <= 0;
       end if;
-    elsif trans_st.write.curr_state = SEND then
+    elsif trans_st.write.state = SEND and not st.read_in_flight then
       if trans_st.write.is_first_word = '1' then 
         local_next_tx_transaction := WRITE_ADD;
       else
         local_next_tx_transaction := WRITE;
       end if;
-      if trans_st.write.curr_inst.seq_mem_access_count > MAX_PKT_SIZE then
+      if trans_st.write.inst.access_count > MAX_PKT_SIZE then
         next_tx_data_size <= MAX_PKT_SIZE;
-      elsif trans_st.write.curr_inst.seq_mem_access_count > 0 then
-        next_tx_data_size <= trans_st.write.curr_inst.seq_mem_access_count;
+      elsif trans_st.write.inst.access_count > 0 then
+        next_tx_data_size <= trans_st.write.inst.access_count;
       else 
         next_tx_data_size <= 0;
       end if;
@@ -400,53 +400,59 @@ begin
     next_tx_transaction <= local_next_tx_transaction;
     next_rx_transaction <= local_next_rx_transaction;
     next_data_out <= local_next_data_out;
-    socbridge_driver_to_ip.valid <= valid_out;
   end process comb_proc;
   -- Process updating internal registers based on primary clock
-  seq_proc: process(ext_to_socbridge_driver_rec.clk, st.ext_to_socbridge_driver_reg.data, rst, clk)
+  seq_proc: process(ext_to_socbridge_driver.control(1), rst, clk)
   begin
     if(rst = '1') then
-      st.ext_to_socbridge_driver_reg.data <= (others => '0');
-      st.socbridge_driver_to_ext_reg.data <= (others => '0');
-      st.socbridge_driver_to_ext_reg.clk <= '0';
-      st.socbridge_driver_to_ext_reg.parity <= '1';
-      st.curr_tx_state <= IDLE;
-      st.curr_rx_state <= IDLE;
-      st.tx_stage <= 0;
-      st.rx_stage <= 0;
-      st.curr_tx_transaction <= NO_OP;
-      st.curr_rx_transaction <= NO_OP;
-      st.tx_data_size <= 0;
-      st.rx_data_size <= 0;
-      st.curr_rx_read_addr <= (others => '0');
-      st.curr_rx_write_addr <= (others => '0');
-      st.curr_write_data <= (others => '0');
-      st.curr_read_data <= (others => '0');
-      socbridge_driver_to_ip.data <= (others => '0');
-      valid_out <= '0';
-
-    elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then
-      st.ext_to_socbridge_driver_reg.data <= ext_to_socbridge_driver_rec.data;
-      st.ext_to_socbridge_driver_reg.clk <= ext_to_socbridge_driver_rec.clk;
-      st.ext_to_socbridge_driver_reg.parity <= ext_to_socbridge_driver_rec.parity;
+      st <= st_reset_vec;
+    elsif(rising_edge(ext_to_socbridge_driver.control(1))) then
+      st.ext_to_socbridge_driver_reg.data <= ext_to_socbridge_driver.payload;
+      -- PARITY CHECK NOT IMPLEMENTED, REMOVING
+      --st.ext_to_socbridge_driver_reg.parity <= ext_to_socbridge_driver_rec.parity;
       st.socbridge_driver_to_ext_reg.data <= next_data_out;
       st.socbridge_driver_to_ext_reg.clk <= not st.socbridge_driver_to_ext_reg.clk;
       st.socbridge_driver_to_ext_reg.parity <= next_parity_out; 
-      st.curr_tx_state <= next_tx_state;
-      st.curr_rx_state <= next_rx_state;
-      valid_out <= '0';
-      case st.curr_tx_state is
+      st.tx_state <= next_tx_state;
+      st.rx_state <= next_rx_state;
+      case st.tx_state is
         when IDLE =>
-          st.curr_tx_transaction <= next_tx_transaction;   
-          st.tx_data_size <= next_tx_data_size;
+          if ip_to_socbridge_driver.flush = '1' then
+            st.last_sent_transaction <= NO_OP;
+          end if;
+          if (next_tx_transaction = WRITE or next_tx_transaction = WRITE_ADD
+          or next_tx_transaction = READ or next_tx_transaction = READ_ADD) then
+            if not st.read_in_flight or not st.write_in_flight then
+              st.tx_transaction <= next_tx_transaction;   
+              st.tx_data_size <= next_tx_data_size;
+            else 
+              st.tx_transaction <= NO_OP;   
+              st.tx_data_size <= 0;
+            end if;
+          else
+            st.tx_transaction <= next_tx_transaction;   
+            st.tx_data_size <= next_tx_data_size;
+          end if;
           if next_tx_transaction = WRITE_ADD or next_tx_transaction = WRITE
           or next_tx_transaction = READ_RESPONSE then
-            st.curr_tx_addr <= trans_st.write.curr_inst.address;
+            st.tx_addr <= trans_st.write.inst.address;
             st.tx_stage <= next_tx_data_size;
           else
-            st.curr_tx_addr <= trans_st.read.curr_inst.address;
+            st.tx_addr <= trans_st.read.inst.address;
             st.tx_stage <= 0;
           end if;
+        when TX_HEADER =>
+          if st.tx_transaction = WRITE or st.tx_transaction = WRITE_ADD then
+            st.last_sent_transaction <= st.tx_transaction;
+            if not (st.rx_state = RX_HEADER and st.rx_transaction = WRITE_ACK) then
+              st.write_in_flight <= true;
+            end if;
+          elsif st.tx_transaction = READ or st.tx_transaction = READ_ADD then
+            st.last_sent_transaction <= st.tx_transaction;
+            if not (st.rx_state = RX_HEADER and st.rx_transaction = READ_RESPONSE) then
+              st.read_in_flight <= true;
+            end if;
+          end if;
         when TX_W_BODY =>
           if st.tx_stage > 0 then
             st.tx_stage <= st.tx_stage - 1;
@@ -457,9 +463,9 @@ begin
           end if;
         when others => 
       end case;
-      case st.curr_rx_state is
+      case st.rx_state is
         when IDLE =>
-          st.curr_rx_transaction <= next_rx_transaction;   
+          st.rx_transaction <= next_rx_transaction;   
           st.rx_data_size <= next_rx_data_size;
           if next_rx_transaction = WRITE_ADD or next_rx_transaction = WRITE
           or next_rx_transaction = READ_RESPONSE then
@@ -468,53 +474,79 @@ begin
             st.rx_stage <= 0;
           end if;
         when RX_HEADER => 
+          if st.rx_transaction = WRITE_ACK then
+            if not (st.tx_state = TX_HEADER and (st.tx_transaction = WRITE or st.tx_transaction = WRITE_ADD)) then
+              st.write_in_flight <= false;
+            end if;
+            if next_rx_transaction /= NO_OP then
+              st.rx_transaction <= next_rx_transaction;   
+              st.rx_data_size <= next_rx_data_size;
+              if next_rx_transaction = WRITE_ADD or next_rx_transaction = WRITE
+              or next_rx_transaction = READ_RESPONSE then
+                st.rx_stage <= next_rx_data_size;
+              else
+                st.rx_stage <= 0;
+              end if;
+            end if;
+          elsif st.rx_transaction = READ_RESPONSE then
+            if not (st.tx_state = TX_HEADER and (st.tx_transaction = READ or st.tx_transaction = READ_ADD)) then
+              st.read_in_flight <= false;
+            end if;
+          end if;
         when RX_R_BODY =>
-          valid_out <= '1';
-          socbridge_driver_to_ip.data <= st.ext_to_socbridge_driver_reg.data;
           if st.rx_stage > 0 then
             st.rx_stage <= st.rx_stage - 1;
           end if;
+          if next_rx_transaction /= NO_OP and st.rx_stage <= 1 then
+            st.rx_transaction <= next_rx_transaction;   
+            st.rx_data_size <= next_rx_data_size;
+            if next_rx_transaction = WRITE_ADD or next_rx_transaction = WRITE
+            or next_rx_transaction = READ_RESPONSE then
+              st.rx_stage <= next_rx_data_size;
+            else
+              st.rx_stage <= 0;
+            end if;
+          end if;
         when RX_W_BODY =>
           if st.rx_stage > 0 then
             st.rx_stage <= st.rx_stage - 1;
-            st.curr_write_data((((st.rx_stage - 1) mod 4) + 1) * 8 - 1 downto ((((st.rx_stage - 1) mod 4) + 1)  - 1) * 8) <= st.ext_to_socbridge_driver_reg.data;
+            st.manager_data(next_slice_32_8_upper(st.rx_stage mod 4) downto next_slice_32_8_lower(st.rx_stage mod 4)) <= st.ext_to_socbridge_driver_reg.data;
           end if;
           if (st.rx_stage - 2) mod 4 = 0 and st.rx_data_size - st.rx_stage > 4 then
-            st.curr_rx_write_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.curr_rx_write_addr) + 4), 32));
+            st.manager_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.manager_addr) + 4), 32));
           end if;
         when RX_AWAIT =>
-          st.curr_read_data <= manager_to_socbridge_driver.data;
-        -- THIS DOESN'T WORK FOR LARGER THAN 4 BYTE ACCESSES, SHOULD BE FIXED BUT NOT NEEDED IF ONLY 4 BYTE ACCESSES ARRIVE
-          if st.curr_tx_transaction = READ_RESPONSE or st.curr_tx_transaction = WRITE_ACK then
-            if (st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD) and (st.tx_stage - 2) mod 4 = 0 then
-              st.curr_rx_read_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.curr_rx_read_addr) + 4), 32));
-            elsif (st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD) and (st.rx_stage - 2) mod 4 = 0 then
-              st.curr_rx_write_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.curr_rx_write_addr) + 4), 32));
+          st.manager_data <= manager_to_socbridge_driver.data;
+          if st.tx_transaction = READ_RESPONSE or st.tx_transaction = WRITE_ACK then
+            if (st.rx_transaction = READ or st.rx_transaction = READ_ADD) and (st.tx_stage - 2) mod 4 = 0 then
+              st.manager_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.manager_addr) + 4), 32));
+            elsif (st.rx_transaction = WRITE or st.rx_transaction = WRITE_ADD) and (st.rx_stage - 2) mod 4 = 0 then
+              st.manager_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.manager_addr) + 4), 32));
             end if;
           end if;
         when ADDR1 =>
-          if st.curr_rx_transaction = READ_ADD then
-            st.curr_rx_read_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
+          if st.rx_transaction = READ_ADD then
+            st.manager_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
           else 
-            st.curr_rx_write_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
+            st.manager_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
           end if;
         when ADDR2 =>
-          if st.curr_rx_transaction = READ_ADD then
-            st.curr_rx_read_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data;
+          if st.rx_transaction = READ_ADD then
+            st.manager_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data;
           else 
-            st.curr_rx_write_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data;
+            st.manager_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data;
           end if;
         when ADDR3 =>
-          if st.curr_rx_transaction = READ_ADD then
-            st.curr_rx_read_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data;
+          if st.rx_transaction = READ_ADD then
+            st.manager_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data;
           else 
-            st.curr_rx_write_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data;
+            st.manager_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data;
           end if;
         when ADDR4 =>
-          if st.curr_rx_transaction = READ_ADD then
-            st.curr_rx_read_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data;
+          if st.rx_transaction = READ_ADD then
+            st.manager_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data;
           else 
-            st.curr_rx_write_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data;
+            st.manager_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data;
           end if;
         when others => 
       end case;
@@ -523,71 +555,77 @@ begin
     --- TRANSLATOR ---
 
     if(rst = '1') then
-      trans_st.read.curr_state <= IDLE;
-      trans_st.read.curr_inst.request <= '0';
-      trans_st.read.curr_inst.address <= (others => '0');
-      trans_st.read.curr_inst.seq_mem_access_count <= 0;
-      trans_st.read.curr_inst.instruction <= NO_OP;
-      trans_st.read.is_first_word <= '1';
-      trans_st.write.curr_state <= IDLE;
-      trans_st.write.curr_inst.request <= '0';
-      trans_st.write.curr_inst.address <= (others => '0');
-      trans_st.write.curr_inst.seq_mem_access_count <= 0;
-      trans_st.write.curr_inst.instruction <= NO_OP;
-      trans_st.write.is_first_word <= '1';
-    elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then
-      trans_st.read.curr_state <= trans_read_next_state;
-      trans_st.write.curr_state <= trans_write_next_state;
-      case trans_st.write.curr_state is
+      trans_st <= translator_reset_vec;
+    elsif(rising_edge(ext_to_socbridge_driver.control(1))) then
+      trans_st.read.state <= trans_read_next_state;
+      trans_st.write.state <= trans_write_next_state;
+      case trans_st.write.state is
         when IDLE =>
-          if controller_to_socbridge_driver.request = '1' and controller_to_socbridge_driver.instruction = WRITE then
-            trans_st.write.curr_inst <= controller_to_socbridge_driver;
+          if controller_to_socbridge_driver.request = '1' and controller_to_socbridge_driver.instruction = WRITE 
+             and trans_st.write.inst.request = '0' then
+            trans_st.write.inst.request <= controller_to_socbridge_driver.request;
+            trans_st.write.inst.address <= controller_to_socbridge_driver.address;
+            trans_st.write.inst.access_count <= controller_to_socbridge_driver.seq_mem_access_count;
           else 
           end if;
           trans_st.write.is_first_word <= '1';
         when SEND =>
+          if trans_st.write.inst.access_count mod 256 = 0 then
+            trans_st.write.is_first_word <= '1';
+          elsif st.last_sent_transaction = READ or st.last_sent_transaction = READ_ADD 
+          or next_tx_transaction = READ or next_tx_transaction = READ_ADD then
+            trans_st.write.is_first_word <= '1';
+          else 
+            trans_st.write.is_first_word <= '0';
+          end if;
         when SEND_ACCEPTED => 
-          trans_st.write.curr_inst.seq_mem_access_count <= trans_st.write.curr_inst.seq_mem_access_count - MAX_PKT_SIZE;
-          trans_st.write.curr_inst.address <= std_logic_vector(unsigned(trans_st.write.curr_inst.address) + MAX_PKT_SIZE);
+          trans_st.write.inst.access_count <= trans_st.write.inst.access_count - MAX_PKT_SIZE;
+          trans_st.write.inst.address <= std_logic_vector(unsigned(trans_st.write.inst.address) + MAX_PKT_SIZE);
         when AWAIT =>
           if  ((ip_to_socbridge_driver.fifo.used_slots = 0 and ip_to_socbridge_driver.flush = '1') 
-              or trans_st.write.curr_inst.seq_mem_access_count <= 0) 
-              and st.curr_tx_state = TX_W_BODY then
-            trans_st.write.curr_inst.request <= '0';
-            trans_st.write.curr_inst.address <= (others => '0');
-            trans_st.write.curr_inst.seq_mem_access_count <= 0;
-            trans_st.write.curr_inst.instruction <= NO_OP;
+              or trans_st.write.inst.access_count <= 0) 
+              and st.tx_state = TX_W_BODY then
+            trans_st.write.inst <= ctrl_inst_reset_vec;
           end if;
-          if trans_st.write.curr_inst.seq_mem_access_count mod 256 = 0 then
+          if trans_st.write.inst.access_count mod 256 = 0 then
             trans_st.write.is_first_word <= '1';
-          elsif trans_st.read.curr_inst.instruction /= NO_OP then
+          elsif st.last_sent_transaction = READ or st.last_sent_transaction = READ_ADD 
+          or next_tx_transaction = READ or next_tx_transaction = READ_ADD then
             trans_st.write.is_first_word <= '1';
           else 
             trans_st.write.is_first_word <= '0';
           end if;
         when others =>
       end case;
-      case trans_st.read.curr_state is
+      case trans_st.read.state is
         when IDLE =>
           if controller_to_socbridge_driver.request = '1' and controller_to_socbridge_driver.instruction = READ then
-            trans_st.read.curr_inst <= controller_to_socbridge_driver;
+            trans_st.read.inst.request <= controller_to_socbridge_driver.request;
+            trans_st.read.inst.address <= controller_to_socbridge_driver.address;
+            trans_st.read.inst.access_count <= controller_to_socbridge_driver.seq_mem_access_count;
           else 
           end if;
           trans_st.read.is_first_word <= '1';
         when SEND =>
-        when SEND_ACCEPTED => 
-          trans_st.read.curr_inst.seq_mem_access_count <= trans_st.read.curr_inst.seq_mem_access_count - MAX_PKT_SIZE;
-          trans_st.read.curr_inst.address <= std_logic_vector(unsigned(trans_st.read.curr_inst.address) + MAX_PKT_SIZE);
-        when AWAIT =>
-          if (ip_to_socbridge_driver.flush = '1' or trans_st.read.curr_inst.seq_mem_access_count <= 0) and st.curr_tx_state = IDLE then
-            trans_st.read.curr_inst.request <= '0';
-            trans_st.read.curr_inst.address <= (others => '0');
-            trans_st.read.curr_inst.seq_mem_access_count <= 0;
-            trans_st.read.curr_inst.instruction <= NO_OP;
-          end if;
-          if trans_st.read.curr_inst.seq_mem_access_count mod 256 = 0 then
+          if trans_st.read.inst.access_count mod 256 = 0 then
             trans_st.read.is_first_word <= '1';
-          elsif trans_st.write.curr_inst.instruction /= NO_OP then
+          elsif st.last_sent_transaction = WRITE or st.last_sent_transaction = WRITE_ADD
+          or next_tx_transaction = WRITE or next_tx_transaction = WRITE_ADD then
+            trans_st.read.is_first_word <= '1';
+          else 
+            trans_st.read.is_first_word <= '0';
+          end if;
+        when SEND_ACCEPTED => 
+          trans_st.read.inst.access_count <= trans_st.read.inst.access_count - MAX_PKT_SIZE;
+          trans_st.read.inst.address <= std_logic_vector(unsigned(trans_st.read.inst.address) + MAX_PKT_SIZE);
+        when AWAIT =>
+          if (ip_to_socbridge_driver.flush = '1' or trans_st.read.inst.access_count <= 0) and st.tx_state = IDLE then
+            trans_st.read.inst <= ctrl_inst_reset_vec;
+          end if;
+          if trans_st.read.inst.access_count mod 256 = 0 then
+            trans_st.read.is_first_word <= '1';
+          elsif st.last_sent_transaction = WRITE or st.last_sent_transaction = WRITE_ADD
+          or next_tx_transaction = WRITE or next_tx_transaction = WRITE_ADD then
             trans_st.read.is_first_word <= '1';
           else 
             trans_st.read.is_first_word <= '0';

src/socbridge/socbridge_driver_pkg.vhd

@@ -8,6 +8,7 @@ use gan_ganimede.io_types.all;
 
 package socbridge_driver_pkg is
   subtype command_size_t is integer range 0 to 128;
+  constant MAX_IN_FLIGHT : integer := 1;
 
   type transaction_t is
     (NO_OP, WRITE_ADD, WRITE, READ_ADD, READ, P_ERR, WRITE_ACK, READ_RESPONSE);
@@ -17,14 +18,20 @@ package socbridge_driver_pkg is
      RX_R_BODY, RX_HEADER, RX_W_BODY);
 
   type tx_state_t is
-    (IDLE, ADDR1, ADDR2, ADDR3, ADDR4, TX_AWAIT, 
+    (IDLE, ADDR1, ADDR2, ADDR3, ADDR4, 
      TX_HEADER, TX_W_BODY, TX_R_BODY);
   --- TRANSLATOR ---
   type ctrl_inst_state_t is (IDLE, SEND, SEND_ACCEPTED, AWAIT);
 
+  type ctrl_inst_t is record
+    request              : std_logic;
+    address              : std_logic_vector(address_width - 1 downto 0);
+    access_count         : integer;
+  end record ctrl_inst_t;
+
   type ctrl_inst_state_rec_t is record
-    curr_inst : controller_to_socbridge_driver_t;
-    curr_state : ctrl_inst_state_t;
+    inst : ctrl_inst_t;
+    state : ctrl_inst_state_t;
     is_first_word : std_logic;
   end record ctrl_inst_state_rec_t;
 
@@ -40,18 +47,19 @@ package socbridge_driver_pkg is
   end record ext_protocol_t;
 
   type state_rec_t is record
-    curr_rx_transaction : transaction_t;
-    curr_tx_transaction : transaction_t;
-    curr_rx_state: rx_state_t;
-    curr_tx_state: tx_state_t;
+    rx_transaction : transaction_t;
+    tx_transaction : transaction_t;
+    rx_state: rx_state_t;
+    tx_state: tx_state_t;
     ext_to_socbridge_driver_reg, socbridge_driver_to_ext_reg : ext_protocol_t; 
     tx_stage, rx_stage : NATURAL;
     tx_data_size, rx_data_size : integer;
-    curr_write_data : std_logic_vector(31 downto 0);
-    curr_read_data : std_logic_vector(31 downto 0);
-    curr_tx_addr : std_logic_vector(31 downto 0);
-    curr_rx_read_addr : std_logic_vector(31 downto 0);
-    curr_rx_write_addr : std_logic_vector(31 downto 0);
+    tx_addr : std_logic_vector(31 downto 0);
+    read_in_flight : boolean;
+    write_in_flight : boolean;
+    last_sent_transaction : transaction_t;
+    manager_addr : std_logic_vector(31 downto 0);
+    manager_data : std_logic_vector(31 downto 0);
   end record state_rec_t;
   impure function calc_parity(
     d : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0)
@@ -64,6 +72,50 @@ package socbridge_driver_pkg is
   pure function get_size_bits(size : command_size_t) return std_logic_vector;
   pure function get_size_bits_sim(size : command_size_t) return std_logic_vector;
   
+  constant ctrl_inst_reset_vec : ctrl_inst_t := (
+    request => '0',
+    address => (others => '0'),
+    access_count => 0
+  );
+
+  constant translator_reset_vec : translator_state_t := (
+      read => (
+        state => IDLE,
+        inst => ctrl_inst_reset_vec,
+        is_first_word => '1'
+    ),
+    write => (
+        state => IDLE,
+        inst => ctrl_inst_reset_vec,
+        is_first_word => '1'
+    )
+  );
+
+  constant ext_protocol_reset_vec : ext_protocol_t := (
+    data => (others => '0'),
+    clk  => '0',
+    parity => '1'
+  );
+
+  constant st_reset_vec : state_rec_t := (
+    ext_to_socbridge_driver_reg => ext_protocol_reset_vec,
+    socbridge_driver_to_ext_reg => ext_protocol_reset_vec,
+    tx_state => IDLE,
+    rx_state => IDLE,
+    tx_stage => 0,
+    rx_stage => 0,
+    tx_transaction => NO_OP,
+    rx_transaction => NO_OP,
+    tx_data_size => 0,
+    rx_data_size => 0,
+    tx_addr => (others => '0'),
+    manager_addr => (others => '0'),
+    manager_data => (others => '0'),
+    read_in_flight  => false,
+    write_in_flight => false,
+    last_sent_transaction => NO_OP
+  );
+
 end package socbridge_driver_pkg;
 
 package body socbridge_driver_pkg is