Adjusted io types for communication between control unit and driver. Also started testbench

Reviewed-on: #11
Reviewed-by: Adam <admag2001@gmail.com>

scripts/build_env.py

@@ -5,57 +5,61 @@ import subprocess
 def getCfFileId(std: str):
     return "08" if std == "08" else "93" ## Weird behaviour from GHDL, but all vhdl versions besides 08 have [...]93.cf
 
-def ghdlEnvExists(std, relativePath="work"):
+def ghdlEnvExists(std, lib):
     ## Check if work exists
     try:
-        os.lstat(relativePath)
+        os.lstat("work")
     except:
         return False
     ## Check that work is writable
-    if not os.access(relativePath, os.W_OK):
+    if not os.access("work", os.W_OK):
-        print(f"{relativePath} is write-protected, please acquire correct permissions")
+        print("work is write-protected, please acquire correct permissions")
         return False
     cfFileExists = False
-    filesInWork = os.listdir(relativePath)
+    filesInWork = os.listdir("work")
     cfFileId = getCfFileId(std)
     for file in filesInWork:
-        if ".cf" in file and cfFileId in file:
+        if ".cf" in file and lib in file and cfFileId in file:
             cfFileExists = True
     if not cfFileExists:
         return False
     ## Nothing bad, continue
     return True
 
-def createBuildEnv(std: str):
+def createBuildEnv(std: str, lib: str):
-    if ghdlEnvExists(std=std):
+    if ghdlEnvExists(std=std, lib=lib):
         print("Build environment already exists, exiting...")
         return -1
     ## Create build env
     print("Initializing GHDL project in current directory...")
     os.makedirs("work",exist_ok=True)
-    addAllVHDLFiles(std=std, init=True)
+    addAllVHDLFiles(std=std, lib=lib, init=True)
     return 0
 
-def addAllVHDLFiles(std: str, init=False):
+def addAllVHDLFiles(std: str, lib: str, init=False):
     ## Ensure everything is ready for adding files 
     ## (init exception to avoid one if-case in ghdlEnvExists)
-    if not ghdlEnvExists(std=std) and not init:
+    if not ghdlEnvExists(std=std, lib=lib) and not init:
        return -1
     vhdlFiles = []
     currentlyAdded = []
+    absWorkDir = os.path.join(os.getcwd(), "work")
     cfFileId = getCfFileId(std)
     ## Find already present files
     if not init:
-        cfFileName = list(filter(lambda x: ".cf" in x and cfFileId in x, os.listdir("work")))[0]
+        cfFileName = list(filter(lambda x: ".cf" in x and lib in x and cfFileId in x, os.listdir(absWorkDir)))[0]
-        cfFilePath = os.path.join(os.getcwd(),f"work/{cfFileName}")
+        cfFilePath = os.path.join(absWorkDir,cfFileName)
         currentlyAdded = getCurrentlyAddedFiles(cfFilePath)
+        print(currentlyAdded)
     ## Add files not added
     for file in os.listdir():
+        print(file)
+        print(currentlyAdded, file, file not in currentlyAdded)
         if ".vhd" in file and file not in currentlyAdded:
-            vhdlFiles.append(file)
+            vhdlFiles.append(os.path.join(os.getcwd(), file))
     if len(vhdlFiles) > 0:
         print(f"Detected new files. Adding {vhdlFiles}")
-        command = ["ghdl", "-i", "--workdir=work", "--work=work", f"--std={std}"] + vhdlFiles
+        command = ["ghdl", "-i", "--workdir=work", f"--work={lib}", f"--std={std}"] + vhdlFiles
         subprocess.run(command)
     return 0
 
@@ -64,5 +68,5 @@ def getCurrentlyAddedFiles(cfFilePath:str):
     lines = f.readlines()
     f.close()
     fileLines = filter(lambda x: "file" in x, lines) 
-    files = map(lambda x: split("\" \"",x)[1], fileLines)
+    files = map(lambda x: split("\"",x)[1], fileLines)
     return list(files)

scripts/elab.py

@@ -1,27 +1,35 @@
 import os
 import subprocess
 import build_env
+from typing import List
 
-def elabDesign(topDef: str, arch: str, lib: str, std: str):
+
+def generateIncludesForGHDL(includes: List[str]):
+    cmd = []
+    for inc in includes:
+        cmd.append(f"-P{os.path.join(os.getcwd(), f"{inc}/work")}")
+    return cmd
+
+def elabDesign(topDef: str, arch: str, lib: str, std: str, includes: List[str]):
     ## Add all source files present in pwd
-    if build_env.addAllVHDLFiles(std) == -1:
+    if build_env.addAllVHDLFiles(std, lib) == -1:
         print("Adding files failed. GHDL Build environment may be broken...")
         return -1
+    incs = generateIncludesForGHDL(includes)
     command = [
-        "ghdl", "-m", f"--workdir={lib}", f"--work={lib}", f"--std={std}",
+        "ghdl", "-m", "--workdir=work", f"--work={lib}", f"--std={std}"] + incs + ["-o", f"work/{topDef}-{arch}", f"work.{topDef}", f"{arch}"]
-        "-o", f"{lib}/{topDef}-{arch}", f"{lib}.{topDef}", f"{arch}"]
     subprocess.run(command)
 
-def runDesign(topDef: str, arch: str, lib: str, std: str):
+def runDesign(topDef: str, arch: str, lib: str, std: str, includes):
     ## elaborate first, then run
-    if elabDesign(topDef, arch, lib, std) == -1:
+    if elabDesign(topDef, arch, lib, std, includes) == -1:
         print("Elaboration failed...")
         return -1
     os.makedirs("wave",exist_ok=True)
     wavePath = os.path.join(os.getcwd(), "wave")
+    incs = generateIncludesForGHDL(includes)
     command = [ ## may add -v for verbose
-        "ghdl", "--elab-run", f"--workdir={lib}", f"--work={lib}", f"--std={std}",
+        "ghdl", "--elab-run", f"--workdir=work", f"--work={lib}", f"--std={std}"] + incs + ["-o", f"work/{topDef}-{arch}", f"{topDef}", f"{arch}", 
-        "-o", f"{lib}/{topDef}-{arch}", f"{topDef}", f"{arch}", 
         f"--wave=wave/{topDef}-{arch}.ghw" ##, "--read-wave-opt=<See"
             ]
     subprocess.run(command)

scripts/gantry.py

@@ -1,7 +1,11 @@
 import typer
 import elab as elaborate
 import build_env
+from typing import List, Optional
 from typing_extensions import Annotated
+import subprocess
+
+gantry_install_path = "/home/thesis2/exjobb-public/scripts" 
 
 app = typer.Typer()
 
@@ -17,32 +21,65 @@ def complete_vhdl_ver():
 
 @software.command(help="Initializes the GHDL build environment in a library named \"work\". Adds all files ending in \".vhd\" to the project")
 def init(
-        std: Annotated[str, typer.Option(help="Which VHDL standard to use. 87, 93, 93c, 00, 02 or 08", autocompletion=complete_vhdl_ver)] = "93c"
+        std: Annotated[str, typer.Option(help="Which VHDL standard to use. 87, 93, 93c, 00, 02 or 08", autocompletion=complete_vhdl_ver)] = "93c",
+        library: Annotated[str, typer.Option("--library", "-l", help="Library to compile from")] = "defaultLib",
         ):
-    return build_env.createBuildEnv(std)
+    return build_env.createBuildEnv(std, library)
 
 
 @software.command(help="Runs analysis and elaboration on the provided top definition and architecture using GHDL. Automatically adds new files not present in the project")
 def elab(
         topdef: Annotated[str, typer.Argument(help="Top Definition entity to synthesize")] = "",
         arch: Annotated[str, typer.Argument(help="Architecture to synthesize within the top definition provided")] = "",
-        library: Annotated[str, typer.Option("--library", "-l", help="Library to compile from")] = "work",
+        library: Annotated[str, typer.Option("--library", "-l", help="Library to compile from")] = "defaultLib",
+        includes: Annotated[Optional[List[str]], typer.Option("--include", "-i", help="Which libraries to include in compile")] = None,
         std: Annotated[str, typer.Option(help="Which VHDL standard to use. 87, 93, 93c, 00, 02 or 08", autocompletion=complete_vhdl_ver)] = "93c"
         ):
-    print(f"Elaborating {topdef} with arch {arch} in library {library}. VHDL {std}")
+    print(f"Elaborating {topdef} with arch {arch} in library {library}. VHDL {std}.")
-    return elaborate.elabDesign(topdef, arch, library, std)
+    if includes is not None:
+        print(f"Including libraries: {includes}")
+    else:
+        includes = []
+    return elaborate.elabDesign(topdef, arch, library, std, includes)
 
 @software.command(help="Simulates elaborated design in GHDL and views waves in gtkwave. Automatically runs `gantry elab` on the same top def and arch.")
 def run(
         topdef: Annotated[str, typer.Argument(help="Top Definition entity to synthesize")] = "",
         arch: Annotated[str, typer.Argument(help="Architecture to synthesize within the top definition provided")] = "",
-        library: Annotated[str, typer.Option("--library", "-l", help="Library to compile from")] = "work",
+        library: Annotated[str, typer.Option("--library", "-l", help="Library to compile from")] = "defaultLib",
+        includes: Annotated[Optional[List[str]], typer.Option("--include", "-i", help="Which libraries to include in compile")] = None,
         std: Annotated[str, typer.Option(help="Which VHDL standard to use. 87, 93, 93c, 00, 02 or 08", autocompletion=complete_vhdl_ver)] = "93c"
         ):
     print(f"Running (and synthesizing if needed) {topdef} with arch {arch} in library {library}. VHDL {std}")
-    return elaborate.runDesign(topdef, arch, library, std)
+    if includes is not None:
+        print(f"Including libraries: {includes}")
+    else:
+        includes = []
+    return elaborate.runDesign(topdef, arch, library, std, includes)
 
-@hardware.command()
+@hardware.command(help="Synthesizes the provided top level design using NXPython. Make sure you run this with NXPython.")
+def synth(
+        topdef: Annotated[str, typer.Argument(help="Top Definition entity to synthesize")] = "",
+        library: Annotated[str, typer.Option("--library", "-l", help="Library to compile from, defaults to \"work\"")] = "defaultLib"
+        ):
+    proc = subprocess.run(["source_and_run.sh", f"{gantry_install_path}/nxp_script.py", "synthDesign", library, topdef])
+
+@hardware.command(help="Places the provided top level design using NXPython. Make sure you run this with NXPython.")
+def place(
+        topdef: Annotated[str, typer.Argument(help="Top Definition entity to synthesize")] = "",
+        library: Annotated[str, typer.Option("--library", "-l", help="Library to compile from, defaults to \"work\"")] = "defaultLib"
+        ):
+    proc = subprocess.run(["source_and_run.sh", f"{gantry_install_path}/nxp_script.py", "placeDesign", library, topdef])
+
+
+@hardware.command(help="Routes the provided top level design using NXPython. Make sure you run this with NXPython.")
+def route(
+        topdef: Annotated[str, typer.Argument(help="Top Definition entity to synthesize")] = "",
+        library: Annotated[str, typer.Option("--library", "-l", help="Library to compile from, defaults to \"work\"")] = "defaultLib"
+        ):
+    proc = subprocess.run(["source_and_run.sh", f"{gantry_install_path}/nxp_script.py", "routeDesign", library, topdef])
+
+@hardware.command(help="")
 def build():
     print("Build!")
 

scripts/install_gantry.sh

@@ -1,6 +1,9 @@
 #!/bin/bash
 
 PWD=$(pwd)
+ESCAPED_PWD=$(printf '%s\n' "$PWD" | sed -e 's/[\/&]/\\&/g')
+echo $ESCAPED_PWD
+sed -i "0,/gantry_install_path =\"\"/s/gantry_install_path = \"\"/gantry_install_path = \"$ESCAPED_PWD\"/" gantry.py
 printf "#!/bin/bash \n$PWD/bin/python3 $PWD/gantry.py \$@" > "$PWD/gantry"
 chmod +x "$PWD/gantry"
 

scripts/nxp_script.py

@@ -0,0 +1,81 @@
+import os
+import subprocess
+import build_env
+import sys
+import traceback
+from nxpython import *
+
+artifact_path = ""
+
+# Evaluate whether we want the user to provide a selection of files
+def makeProject(library: str, project_name: str, path):
+    # Create an Impulse project and add all VHDL files to it
+    print(path)
+    #Createproject enters the implicitly created directory
+    print(f"Creating project \'{project_name}\'\n")
+    getProject().setTopCellName(library, project_name)
+    getProject().setVariantName("NG-MEDIUM", "LGA-625")
+    getProject().addParameters({})
+    print(path)
+    listed = list(os.listdir(path))
+    files = list(filter(lambda x: ".vhdl" in x or ".vhd" in x or ".v\0" in x, listed)) # Find VHDL and Verilog files
+    files = list(map(lambda x: os.path.join(path, x), files))
+    print(f"Adding the following files to project: {files}\n")
+    getProject().addFiles(files)
+    print("Saving project")
+    getProject().save(os.path.join(artifact_path, project_name + ".nym"))
+    return 0
+
+# Do we want the user to specify how far they want to progress wach step? What does the number mean?
+def synthDesign(library: str, project_name: str, path):
+    # Synthesize the design of the project of the provided `project_name`
+    print("Starting synthesis\n")
+    try:
+        nymFile = os.path.join(artifact_path, project_name + ".nym")
+        os.lstat(nymFile)
+        getProject().loadNative(nymFile)
+    except:
+        print("No existing project found, creating new project\n")
+        makeProject(library, project_name, path)
+        getProject().loadNative(os.path.join(artifact_path, project_name + ".nym"))
+    getProject().progress("Synthesize", 3)
+    getProject().save(os.path.join(artifact_path,  project_name + "-synth.nym"))
+    return 0
+
+def placeDesign(library: str, project_name: str, path):
+    # Place the given design. Will use a previously synthesized project if available, otherwise one will be created. 
+    print("Starting place\n")
+    try:
+        nymFile = os.path.join(artifact_path, project_name + "-synth.nym")
+        os.lstat(nymFile)
+        getProject().load(nymFile)
+    except:
+        print("No existing synthesis found, entering synthesis stage\n")
+        synthDesign(library, project_name, path)
+        getProject().load(os.path.join(artifact_path, project_name + "-synth.nym"))
+    getProject().progress("Place", 5)
+    getProject().save(os.path.join(artifact_path, project_name + "-place.nym"))
+
+def routeDesign(library: str, project_name: str, path):
+    # Route the given design. Will use a previously placed project if available, otherwise one will be created.
+    print("Starting route\n")
+    try:
+        nymFile = os.path.join(artifact_path, project_name + "-place.nym")
+        os.lstat(nymFile)
+        getProject().load(nymFile)
+    except:
+        print("No existing place found, entering place stage\n")
+        placeDesign(library, project_name, path)
+        getProject().load(os.path.join(artifact_path, project_name + "-place.nym"))
+    getProject().progress("Route", 3)
+    getProject().save(os.path.join(artifact_path, project_name + "-route.nym"))
+
+
+if __name__ == "__main__":
+    path = os.getcwd()
+    artifact_path = os.path.join(path, "syn")
+    print(f"Calling {sys.argv[1]}() with arguments {sys.argv[2]}, {sys.argv[3]}")
+    createProject(artifact_path)
+    globals()[sys.argv[1]](sys.argv[2], sys.argv[3], path)
+    getProject().createAnalyzer()
+    getProject().getAnalyzer().launch(conditions="worstcase", maximumSlack=0, searchPathsLimit=10, synthesisMode=False)

scripts/source_and_run.sh

@@ -0,0 +1,6 @@
+#!/bin/bash
+
+source /gsl/cad/modules/init/bash
+
+module add /gsl/cad/modules/modulefiles/nanoxplore/nxdesignsuite/24.3.0.0
+nxpython $@

src/control_socbridge_tb.vhd

@@ -0,0 +1,24 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+library work;
+use work.io_types.all;
+use work.socbridge_driver_tb_pkg.all;
+
+entity control_socbridge_tb is
+end entity control_socbridge_tb;
+
+architecture tb of control_socbridge_tb is
+  
+begin
+
+  clock_proc: process
+  begin
+  for i in 0 to 50 loop
+    wait for cycle / 2;
+    clock <= not clock;
+  end loop;
+  wait;
+  end process clock_proc;
+  
+end architecture tb;

src/control_unit.vhd

@@ -0,0 +1,68 @@
+library IEEE;  
+use IEEE.std_logic_1164.all;
+use IEEE.MATH_REAL.all;
+library work;
+use work.io_types.all;
+
+entity control_unit is
+  
+  port (
+    clk, rst        : in  std_logic;
+    ext_control_in  : in  ext_control_unit_in_t;
+    ext_control_out : out ext_control_unit_out_t;
+    int_control_in  : in  int_control_unit_in_t;
+    int_control_out : out int_control_unit_out_t;
+  );
+
+end entity control_unit;
+
+architecture behave of control_unit is
+  type state_t is record
+    address: std_logic_vector(address_width - 1 downto 0);
+    seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
+    curr_driver: std_logic_vector(number_of_drivers - 1 downto 0); --one-hot encoded, 0 means disabled
+    ready: std_logic;
+    instruction: std_logic_vector(inst_word_width - 1 downto 0);
+  end record state_t;
+
+  signal state: state_t;
+  shared variable ored: std_logic;
+  
+
+begin
+
+  comb_proc: process(control_in, state)
+  begin
+    ored := '0';
+    ready_reduction: for i in 0 to number_of_drivers - 1 loop
+      ored := ored or int_control_in.active_driver(i);
+    end loop ready_reduction;
+    int_control_out.driver_id <= state.curr_driver;
+    int_control_out.address <= state.address;
+    int_control_out.seq_mem_access_count <= state.seq_mem_access_count;        
+    int_control_out.ready <= state.ready;
+    int_control_out.instruction <= state.instruction;
+  end process comb_proc;
+
+  sync_proc: process(clk, state)
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        state <= ((others => '0'), 
+                  (others => '0'), 
+                  (others => '0'),
+                  '1',
+                  x"00");
+      else
+        state.ready <= not ored;
+        if ored = '0' then
+          state.address <= ext_control_in.address;
+          state.seq_mem_access_count <= ext_control_in.seq_mem_access_count;
+          state.curr_driver <= ext_control_in.driver_id;
+          state.instruction <= ext_control_in.instruction;
+        end if;
+      end if;
+    end if;
+  end process sync_proc;
+  
+end architecture behave;

src/control_unit_tb.vhd

@@ -0,0 +1,91 @@
+library IEEE;  
+use IEEE.std_logic_1164.all;
+use IEEE.MATH_REAL.all;
+use ieee.numeric_std.all;
+library work;
+use work.io_types.all;
+
+entity control_unit_tb is
+end entity control_unit_tb;
+
+architecture tb of control_unit_tb is
+
+  constant cycle: Time := 10 ns;
+  signal clock: std_logic := '0';
+  signal reset: std_logic := '0';
+  signal control_input: control_unit_in_t := (
+                                              (others => '0'),
+                                              (others => '0'),
+                                              (others => '0'),
+                                              (others => '0'),
+                                              x"00");
+  signal control_output: control_unit_out_t := (
+                                              (others => '0'),
+                                              (others => '0'),
+                                              (others => '1'),
+                                              '1',
+                                              x"00");
+  signal current_driver : std_logic_vector(2 downto 0) := "000";
+  shared variable word_counter: natural := 0;
+
+begin
+  
+  clock_proc: process
+  begin
+  for i in 0 to 50 loop
+    wait for cycle / 2;
+    clock <= not clock;
+  end loop;
+  wait;
+  end process clock_proc;
+
+  control_unit_inst: entity work.control_unit
+    port map(
+      clk => clock,
+      rst => reset,
+      control_in => control_input,
+      control_out => control_output
+    );
+
+stimulus_proc: process
+begin
+  wait for cycle;
+
+  control_input.driver_id <= "010";
+  control_input.active_driver <= "000";
+  control_input.address <= x"F0F0F0F0";
+  control_input.seq_mem_access_count <= "00000011";
+  control_input.instruction <= x"81";
+  word_counter := 3;
+  wait for cycle;
+  current_driver <= "010";
+  
+  report "entering loop with word_counter" & integer'image(word_counter);
+  for_loop: for i in word_counter - 1 downto 0 loop
+    wait for cycle;
+    report "words remaining are " & integer'image(i);
+  end loop for_loop;
+  
+  control_input.active_driver <= "000";
+  report "Stim process done";
+  wait;
+end process stimulus_proc; 
+
+monitor_proc: process
+begin
+
+  wait for cycle;
+
+  wait for cycle;
+  assert control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity error;
+  assert control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error;
+  assert control_output.instruction = x"81" report "Incorrect memory op from control_unit" severity error;
+
+  wait for 5 * cycle;
+  reset <= '1';
+
+  report "Monitor process done";
+  wait;
+end process monitor_proc;
+
+end architecture tb;

src/ganimede.vhd

@@ -0,0 +1,74 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+library work;
+use work.io_types.all;
+
+entity ganimede is
+  port (
+    clk                 : in std_logic;
+    reset               : in std_logic;
+    ext_interface_in    : in ext_interface_in_t;
+    ext_interface_out   : out ext_interface_out_t;
+    int_interface_in    : in int_interface_in_t;
+    int_interface_out   : out int_interface_out_t
+  );
+end entity ganimede;
+architecture rtl of ganimede is
+  --- SIGNAL DECLERATIONS ---
+  signal gan_int_interface_in  : int_interface_in_t;
+  signal gan_int_interface_out : int_interface_out_t;
+  signal gan_ext_interface_in  : ext_interface_in_t;
+  signal gan_ext_interface_out : ext_interface_out_t;
+
+  --signal gan_socbridge_WE_in : std_logic;
+  --signal gan_socbridge_WE_out : std_logic;
+  --signal gan_socbridge_is_full_in : std_logic;
+  --signal gan_socbridge_is_full_out : std_logic;
+  
+  --- COMPONENT DECLERATIONS ---
+  --component fifo is 
+  --  generic(
+  --    WIDTH : positive;
+  --    DEPTH : positive
+  --  );
+  --  port(
+  --    clk, reset, read_enable, write_enable : in std_logic;
+  --    is_full, is_empty                     : out std_logic;
+  --    data_in      : in std_logic_vector(WIDTH - 1 downto 0);
+  --    data_out     : out std_logic_vector(WIDTH - 1 downto 0)
+  --  );
+  --end component;
+
+  component socbridge_driver is
+    port(
+      clk     : in std_logic;
+      reset   : in std_logic;
+      ext_in  : in ext_socbridge_in_t;
+      ext_out : out ext_socbridge_out_t;
+      int_in  : out int_socbridge_in_t;
+      int_out : in int_socbridge_out_t
+    );
+  end component;
+
+begin
+  --- CONNECT EXTERNAL SIGNALS TO INTERNAL CONNECTIONS ---
+  gan_int_interface_in  <= int_interface_in;
+  int_interface_out     <= gan_int_interface_out;
+  gan_ext_interface_in  <= ext_interface_in;
+  ext_interface_out     <= gan_ext_interface_out;
+  
+  --- DRIVER INSTANTIATION ---
+  socbridge_driver_inst: socbridge_driver
+   port map(
+      clk     => clk,
+      reset   => reset,
+      ext_in  => gan_ext_interface_in.socbridge,
+      ext_out => gan_ext_interface_out.socbridge,
+      int_in  => gan_int_interface_in.socbridge,
+      int_out => gan_int_interface_out.socbridge
+  );
+
+  --- LATER WE ADD OPTIMIZATIONS HERE ---
+
+
+end architecture rtl;

src/io_type_pkg.vhd

@@ -4,16 +4,13 @@ use IEEE.MATH_REAL.all;
 
 package io_types is
   
+  --- CONSTANTS ---
+  constant number_of_drivers: natural := 3;
+  constant address_width: natural := 32;
+  constant seq_vector_length: natural := 8;
+  constant inst_word_width: natural := 8;
+
   --- STANDARD TYPES ---
-  type ext_protocol_impl_t is record 
-    payload, control: STD_LOGIC_VECTOR;
-  end record ext_protocol_impl_t;
-
-  type int_protocol_impl_t is record
-    payload : STD_LOGIC_VECTOR;
-  -- ADD MORE STUFF WHEN WE HAVE DECIDED UPON DRIVER INTERFACE
-  end record int_protocol_impl_t;
-
   type ext_protocol_def_t is record
     name: string (1 to 20);
     payload_width: natural;
@@ -22,46 +19,70 @@ package io_types is
 
   type interface_inst_t is record
     socbridge: ext_protocol_def_t;
-    spi: ext_protocol_def_t;
   end record interface_inst_t;
 
+    type ext_control_unit_in_t is record
+    driver_id: std_logic_vector(number_of_drivers - 1 downto 0);
+    address: std_logic_vector(address_width - 1 downto 0);
+    seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
+    instruction: std_logic_vector(inst_word_width - 1 downto 0);
+  end record control_unit_in_t;
+
+  type ext_control_unit_out_t is record
+    ready: std_logic;
+  end record ext_control_unit_out_t;
+
+  type int_control_unit_out_t is record
+    driver_id: std_logic_vector(number_of_drivers - 1 downto 0);
+    address: std_logic_vector(address_width - 1 downto 0);
+    seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
+    instruction: std_logic_vector(inst_word_width - 1 downto 0);
+  end record control_unit_out_t;
+
+  type int_control_unit_in_t is record
+    active_driver: std_logic_vector(number_of_drivers - 1 downto 0)
+  end record int_control_unit_out_t;
+
   --- PROTOCOL INFORMATION ---
   constant interface_inst : interface_inst_t := (
-    ("SoCBridge           ", 8, 2, 2),
+    socbridge => ("SoCBridge           ", 8, 2, 2)
-    ("SPI                 ", 1, 3, 3)
   ); 
 
   --- AUTOGENERATED TYPES ---
+  type ext_socbridge_in_t is record 
+    payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
+    control : STD_LOGIC_VECTOR(interface_inst.socbridge.control_width_in - 1 downto 0);
+  end record ext_socbridge_in_t;
+
+  type ext_socbridge_out_t is record 
+    payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
+    control : STD_LOGIC_VECTOR(interface_inst.socbridge.control_width_in - 1 downto 0);
+  end record ext_socbridge_out_t;
+
+  type int_socbridge_in_t is record 
+    payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
+    write_enable_in, is_full_out : std_logic;
+  end record int_socbridge_in_t;
+
+  type int_socbridge_out_t is record 
+    payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
+    write_enable_out, is_full_in : std_logic;
+  end record int_socbridge_out_t;
+
   type ext_interface_in_t is record
-    socbridge : ext_protocol_impl_t( 
+    socbridge : ext_socbridge_in_t;     
-      payload(interface_inst.socbridge.payload_width - 1 downto 0),
-      control(interface_inst.socbridge.control_width_in - 1 downto 0));
-    spi : ext_protocol_impl_t(
-      payload(interface_inst.spi.payload_width - 1 downto 0),
-      control(interface_inst.spi.control_width_in - 1 downto 0));
   end record ext_interface_in_t;
 
   type ext_interface_out_t is record
-    socbridge : ext_protocol_impl_t( 
+    socbridge : ext_socbridge_out_t;
-      payload(interface_inst.socbridge.payload_width - 1 downto 0),
-      control(interface_inst.socbridge.control_width_out - 1 downto 0));
-    spi : ext_protocol_impl_t(
-      payload(interface_inst.spi.payload_width - 1 downto 0),
-      control(interface_inst.spi.control_width_out - 1 downto 0));
   end record ext_interface_out_t;
 
   type int_interface_in_t is record
-    socbridge : int_protocol_impl_t(
+    socbridge : int_socbridge_in_t;
-      payload(interface_inst.socbridge.payload_width - 1 downto 0));
-    spi : int_protocol_impl_t(
-      payload(interface_inst.spi.payload_width - 1 downto 0));
   end record int_interface_in_t;
 
   type int_interface_out_t is record
-    socbridge : int_protocol_impl_t(
+    socbridge : int_socbridge_out_t;
-      payload(interface_inst.socbridge.payload_width - 1 downto 0));
-    spi : int_protocol_impl_t(
-      payload(interface_inst.spi.payload_width - 1 downto 0));
   end record int_interface_out_t;
 
 end package io_types;

src/socbridge_driver.vhd

@@ -0,0 +1,292 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+library work;
+use work.io_types.all;
+use work.socbridge_driver_tb_pkg.all;
+
+
+entity socbridge_driver is
+  port(
+    clk     : in std_logic;
+    rst     : in std_logic;
+    cmd     : in command_t;
+    address : in std_logic_vector(31 downto 0);
+    cmd_size: in positive;
+    ext_in  : in ext_socbridge_in_t;
+    ext_out : out ext_socbridge_out_t;
+    int_in  : out int_socbridge_in_t;
+    int_out : in int_socbridge_out_t
+  );
+end entity socbridge_driver;
+
+architecture rtl of socbridge_driver is
+  
+  signal next_parity_out : std_logic;
+  signal ext_in_rec : ext_protocol_t;
+  shared variable ext_out_data_cmd : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
+  signal test : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
+  signal next_state : state_t;
+  signal curr_cmd_bits : std_logic_vector(4 downto 0);
+  signal curr_response : response_t;
+  signal curr_response_bits : std_logic_vector(4 downto 0);
+  signal st : state_rec_t;
+begin
+  --- DEBUG GLOBAL BINDINGS ---
+  -- synthesis translate_off
+  G_next_parity_out <= next_parity_out;
+  G_ext_in_rec <= ext_in_rec;
+  G_next_state <= next_state;
+  G_ext_out_data_cmd <=test;
+  G_curr_command_bits <= curr_cmd_bits;
+  G_curr_response <= curr_response;
+  G_curr_response_bits <= curr_response_bits;
+  G_st <= st;
+  -- synthesis translate_on
+  ext_in_rec.data <= ext_in.payload;
+  ext_in_rec.clk <= ext_in.control(1);
+  ext_in_rec.parity <= ext_in.control(0);
+
+  -- Helpful Bindings --
+  curr_response_bits <= ext_in.payload(7 downto 3); -- CANT USE EXT_IN_REC here for some reason, the assignment becomes stasteful
+                                                    -- Not sure that the two process method is helping here: if this was a normal
+                                                    -- signal assignment there would be no confusion.
+                                                    -- in the case ... <= ext_in_rec we get
+                                                    -- curr_resp | ext_in_rec | ext_in
+                                                    -- 00000     | 00000000   | 00001001 
+                                                    -- 00000     | 00001001   | 00001001 
+                                                    -- 00001     | 00001001   | 00001001 
+                                                    -- 00001     | 00001001   | 00001001 
+                                                    -- 
+                                                    -- but in the case ... <= ext_in we get
+                                                    -- curr_resp | ext_in_rec | ext_in
+                                                    -- 00000     | 00000000   | 00001001 
+                                                    -- 00001     | 00001001   | 00001001 
+                                                    -- 00001     | 00001001   | 00001001 
+                                                    -- 00001     | 00001001   | 00001001 
+                                                  
+  with curr_response_bits select
+    curr_response <= WRITE_ACK when "00001",
+                      WRITE_ACK when "00101",
+                      READ_RESPONSE when "01000",
+                      READ_RESPONSE when "01100",
+                      NO_OP when others;
+  comb_proc: process(ext_in, int_out, curr_response, st, cmd)
+  begin
+    -- Outputs 
+    ext_out <= create_io_type_out_from_ext_protocol(st.ext_out_reg);
+
+
+    --- State Transition Diagram ---
+--                                                            
+--                                               
+--                                               
+--           +-----+                                     
+--           |     |                                             
+--          \|/ /--+                                             
+--          IDLE<-------------------+                 
+--          /  \                    |                            
+--         /     \                  |                            
+--        /       \                 |                            
+--      \|/       \|/               |                         
+--  TX_HEADER   RX_HEADER           |                        
+--       |\     /    |              |                           
+--       | \   /     |              |                           
+--       |  ADDR1    |              |                           
+--       |    |      |              |                           
+--       |   \|/     |              |                           
+--       |  ADDR2    |              |                           
+--       |    |      |              |                           
+--       |   \|/     |              |                           
+--       |  ADDR3    |              |                           
+--       |    |      |              |                           
+--       |   \|/     |              |                           
+--       |  ADDR4    |              |                           
+--       |   /\      |              |                           
+--       |  /  \     |              |                           
+--       |-+    +----|     +---+    |                           
+--      \|/         \|/   \|/  |    |                           
+--   TX_BODY     RX_RESPONSE---+    |                           
+--       |           |              |                           
+--       |  +--+     |              |                           
+--      \|/\|/ |    \|/             |                           
+--     TX_ACK--+ RX_BODY            |                           
+--       |           |              |                           
+--       |           |              |                           
+--       +-----------+--------------+                 
+--                                                            
+  --- Next State Assignment --- 
+    case st.curr_state is
+      when IDLE => 
+        if cmd = WRITE or cmd = WRITE_ADD then
+          next_state <= TX_HEADER;
+        elsif cmd = READ or cmd = READ_ADD then
+          next_state <= RX_HEADER;
+        else
+          next_state <= IDLE;
+        end if;
+      when TX_HEADER =>
+      -- The header only takes one word (cycle) to transmit.
+      -- Continue to body or address directly afterwards. 
+        if st.cmd_reg = WRITE_ADD then
+          next_state <= ADDR1;
+        else 
+          next_state <= TX_BODY;
+        end if;
+      when TX_BODY =>
+      -- Here we want to stay in TX_BODY for the duration of a packet.
+        if st.write_stage = 0 then
+          next_state <= TX_ACK;
+        else 
+          next_state <= TX_BODY;
+        end if;
+      when TX_ACK =>
+      -- Wait for write acknowledgement. 
+        if curr_response = WRITE_ACK then
+          next_state <= IDLE;
+        else 
+          next_state <= TX_ACK;
+        end if;
+      when RX_HEADER =>
+      -- The header only takes one word (cycle) to transmit.
+      -- Continue to awaiting response directly afterwards.
+        if st.cmd_reg = READ_ADD then
+          next_state <= ADDR1;
+        else 
+          next_state <= RX_RESPONSE;
+        end if;
+      when RX_RESPONSE =>
+      -- Wait for read response. 
+        if curr_response = READ_RESPONSE then
+          next_state <= RX_BODY_NO_OUT;
+        else 
+          next_state <= RX_RESPONSE;
+        end if;
+      when RX_BODY_NO_OUT => 
+        next_state <= RX_BODY;
+      when RX_BODY =>
+      -- Here we want to stay in RX_BODY for the duration of a packet.
+        if st.read_stage = 0 then
+          next_state <= IDLE;
+        else 
+          next_state <= RX_BODY;
+        end if;
+      when ADDR1 =>
+      -- Transmits the entire address and returns to the appropriate 
+        next_state <= ADDR2;
+      when ADDR2 =>
+        next_state <= ADDR3;
+      when ADDR3 =>
+        next_state <= ADDR4;
+      when ADDR4 => 
+        if st.cmd_reg = WRITE or st.cmd_reg = WRITE_ADD then 
+          next_state <= TX_BODY;
+        else 
+          next_state <= RX_RESPONSE;
+        end if;
+    end case;
+    
+  --- Combinatorial output based on current state ---
+    ext_out_data_cmd := (others => '0');
+    int_in.is_full_out <= '1';
+    int_in.write_enable_in <= '0';
+    int_in.payload <= (others => '0');
+    case st.curr_state is
+      when IDLE => 
+        if cmd = WRITE or cmd = WRITE_ADD then
+          ext_out_data_cmd := get_cmd_bits(cmd) & get_size_bits(cmd_size);
+        elsif cmd = READ or cmd = READ_ADD then
+          ext_out_data_cmd := get_cmd_bits(cmd) & get_size_bits(cmd_size);
+        end if;       
+      when TX_HEADER =>
+        if st.cmd_reg = WRITE_ADD then
+          ext_out_data_cmd := st.addr_reg(7 downto 0);
+        else 
+          ext_out_data_cmd := int_out.payload;
+          int_in.is_full_out <= '0';
+        end if;
+      when TX_BODY =>
+        if st.write_stage > 0 then
+          int_in.is_full_out <= '0';
+          ext_out_data_cmd := int_out.payload;
+        else 
+          ext_out_data_cmd := (others => '0');
+        end if;
+      when TX_ACK =>
+      when RX_HEADER =>
+        if st.cmd_reg = READ_ADD then
+          ext_out_data_cmd := st.addr_reg(7 downto 0);
+        end if; 
+      when RX_RESPONSE =>
+      when RX_BODY_NO_OUT => 
+      when RX_BODY =>
+        int_in.payload <= st.ext_in_reg.data;
+        int_in.write_enable_in <= '1';
+      when ADDR1 =>
+        ext_out_data_cmd := st.addr_reg(15 downto 8);
+      when ADDR2 =>
+        ext_out_data_cmd := st.addr_reg(23 downto 16);
+      when ADDR3 =>
+        ext_out_data_cmd := st.addr_reg(31 downto 24);
+      when ADDR4 =>
+        if st.cmd_reg = WRITE_ADD then
+          int_in.is_full_out <= '0';
+          ext_out_data_cmd := int_out.payload;
+        end if;
+    end case;
+    next_parity_out <= calc_parity(ext_out_data_cmd);
+    --- DEBUG GLOBAL BINDINGS ---
+    -- synthesis translate_off
+    test <= ext_out_data_cmd;
+    -- synthesis translate_on
+  end process comb_proc;
+  -- Process updating internal registers based on primary clock
+  seq_proc: process(ext_in_rec.clk, rst)
+  begin
+    if(rst = '1') then
+      st.ext_in_reg.data <= (others => '0');
+      st.ext_out_reg.data <= (others => '0');
+      st.ext_out_reg.clk <= '0';
+      st.ext_out_reg.parity <= '1';
+      st.curr_state <= IDLE;
+      st.write_stage <= 0;
+      st.read_stage <= 0;
+      st.cmd_reg <= NO_OP;
+      st.addr_reg <= (others => '0');
+
+    elsif(rising_edge(ext_in_rec.clk)) then
+      st.ext_in_reg.data <= ext_in_rec.data;
+      st.ext_in_reg.clk <= ext_in_rec.clk;
+      st.ext_in_reg.parity <= ext_in_rec.parity;
+      st.ext_out_reg.data <= ext_out_data_cmd;
+      st.ext_out_reg.clk <= not st.ext_out_reg.clk;
+      st.ext_out_reg.parity <= next_parity_out; 
+      st.curr_state <= next_state;
+      case st.curr_state is
+        when IDLE =>
+          if cmd = WRITE or cmd = WRITE_ADD or
+             cmd = READ  or cmd = READ_ADD then
+            st.addr_reg <= address;
+            st.cmd_reg <= cmd; 
+          end if;
+        when TX_HEADER =>
+          st.write_stage <= 2**(cmd_size - 1) - 1;
+        when TX_BODY =>
+          if st.write_stage > 0 then
+            st.write_stage <= st.write_stage - 1;
+          end if;
+        when RX_HEADER =>
+          st.read_stage <= 2**(cmd_size - 1) - 1;
+        when RX_BODY =>
+          if st.read_stage > 0 then
+            st.read_stage <= st.read_stage - 1;
+          end if;
+        when others => 
+      end case;
+    end if;
+      
+  end process seq_proc;
+
+
+
+end architecture rtl;

src/socbridge_driver_tb.gtkw

@@ -0,0 +1,77 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Feb 27 10:27:13 2025
+[*]
+[dumpfile] "/home/thesis1/repos/exjobb-public/src/wave/socbridge_driver_tb-tb.ghw"
+[dumpfile_mtime] "Thu Feb 27 10:26:19 2025"
+[dumpfile_size] 2417
+[savefile] "/home/thesis1/repos/exjobb-public/src/socbridge_driver_tb.gtkw"
+[timestart] 21800000
+[size] 956 1033
+[pos] -1 -1
+*-24.456779 22000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] top.
+[treeopen] top.socbridge_driver_tb.
+[treeopen] top.socbridge_driver_tb_pkg.
+[treeopen] top.socbridge_driver_tb_pkg.g_st.
+[sst_width] 273
+[signals_width] 214
+[sst_expanded] 1
+[sst_vpaned_height] 324
+@800200
+-Outwards
+-Internal
+@28
+top.socbridge_driver_tb.int_out.is_full_in
+@22
+#{top.socbridge_driver_tb.int_out.payload[7:0]} top.socbridge_driver_tb.int_out.payload[7] top.socbridge_driver_tb.int_out.payload[6] top.socbridge_driver_tb.int_out.payload[5] top.socbridge_driver_tb.int_out.payload[4] top.socbridge_driver_tb.int_out.payload[3] top.socbridge_driver_tb.int_out.payload[2] top.socbridge_driver_tb.int_out.payload[1] top.socbridge_driver_tb.int_out.payload[0]
+@28
+top.socbridge_driver_tb.int_out.write_enable_out
+@1000200
+-Internal
+@800200
+-External
+@28
++{clk} top.socbridge_driver_tb.ext_out.control[1]
++{parity} top.socbridge_driver_tb.ext_out.control[0]
++{next_parity} top.socbridge_driver_tb_pkg.g_next_parity_out
+@22
+#{top.socbridge_driver_tb.ext_out.payload[7:0]} top.socbridge_driver_tb.ext_out.payload[7] top.socbridge_driver_tb.ext_out.payload[6] top.socbridge_driver_tb.ext_out.payload[5] top.socbridge_driver_tb.ext_out.payload[4] top.socbridge_driver_tb.ext_out.payload[3] top.socbridge_driver_tb.ext_out.payload[2] top.socbridge_driver_tb.ext_out.payload[1] top.socbridge_driver_tb.ext_out.payload[0]
++{next_payload[7:0]} #{top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[7:0]} top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[7] top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[6] top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[5] top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[4] top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[3] top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[2] top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[1] top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[0]
+@1000200
+-External
+-Outwards
+@800200
+-Inwards
+-Internal
+@28
+top.socbridge_driver_tb.int_in.is_full_out
+@22
+#{top.socbridge_driver_tb.int_in.payload[7:0]} top.socbridge_driver_tb.int_in.payload[7] top.socbridge_driver_tb.int_in.payload[6] top.socbridge_driver_tb.int_in.payload[5] top.socbridge_driver_tb.int_in.payload[4] top.socbridge_driver_tb.int_in.payload[3] top.socbridge_driver_tb.int_in.payload[2] top.socbridge_driver_tb.int_in.payload[1] top.socbridge_driver_tb.int_in.payload[0]
+@28
+top.socbridge_driver_tb.int_in.write_enable_in
+@1000200
+-Internal
+@800200
+-External
+@28
++{clk} top.socbridge_driver_tb.ext_in.control[1]
++{parity} top.socbridge_driver_tb.ext_in.control[0]
+@22
+#{top.socbridge_driver_tb.ext_in.payload[7:0]} top.socbridge_driver_tb.ext_in.payload[7] top.socbridge_driver_tb.ext_in.payload[6] top.socbridge_driver_tb.ext_in.payload[5] top.socbridge_driver_tb.ext_in.payload[4] top.socbridge_driver_tb.ext_in.payload[3] top.socbridge_driver_tb.ext_in.payload[2] top.socbridge_driver_tb.ext_in.payload[1] top.socbridge_driver_tb.ext_in.payload[0]
+@1000200
+-External
+-Inwards
+@800200
+-Internal Signals
+@420
+top.socbridge_driver_tb_pkg.g_st.curr_state
++{next_state} top.socbridge_driver_tb_pkg.g_next_state
+top.socbridge_driver_tb_pkg.g_curr_command
+top.socbridge_driver_tb_pkg.g_curr_respoonse
+@1000200
+-Internal Signals
+@420
+top.socbridge_driver_tb.cmd
+[pattern_trace] 1
+[pattern_trace] 0

src/socbridge_driver_tb.vhd

@@ -0,0 +1,337 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.MATH_REAL.all;
+library work;
+use work.io_types.all;
+use work.socbridge_driver_tb_pkg.all;
+
+
+entity socbridge_driver_tb is
+end entity socbridge_driver_tb;
+
+architecture tb of socbridge_driver_tb is
+  signal clk : std_logic := '0';
+  signal rst : std_logic;
+  signal cmd : command_t;
+  signal address : std_logic_vector(31 downto 0);
+  signal cmd_size : positive;
+  signal ext_in  :  ext_socbridge_in_t;
+  signal ext_out :  ext_socbridge_out_t;
+  signal int_in  :  int_socbridge_in_t;
+  signal int_out :  int_socbridge_out_t;
+  signal curr_word : std_logic_vector(ext_in.payload'length - 1 downto 0);
+  signal expected_out : std_logic_vector(ext_out.payload'length - 1 downto 0);
+  
+  constant CLK_PERIOD : TIME := 10 ns;
+  constant SIMULATION_CYCLE_COUNT : INTEGER := 100;
+
+  procedure fail(error_msg : string) is 
+  begin
+    wait for CLK_PERIOD;
+    report "Simulation ending due to: " & error_msg & ". Shutting down..." severity FAILURE;
+  end procedure;
+
+  procedure check_next_state(correct_state: state_t) is
+  begin
+    if(not (correct_state = G_next_state)) then
+      report "Next State is not what was expected, found " & state_t'image(G_next_state)
+            & " but expected " & state_t'image(correct_state) severity error;
+      fail("Next State");
+    end if;
+  end procedure;
+  
+  procedure check_data_out(correct_data: std_logic_vector(ext_out.payload'length - 1 downto 0)) is
+  begin
+    if(not (correct_data = ext_out.payload)) then
+      report "Data out is not what was expected, found " & to_string(ext_out.payload)
+            & " but expected " & to_string(correct_data) severity error;
+      fail("Data out");
+    end if;
+  end procedure;
+
+  procedure check_parity(correct_data: std_logic_vector(ext_out.payload'length - 1 downto 0)) is
+  begin
+    if(not (calc_parity(correct_data) = calc_parity(ext_out.payload))) then
+      report "Parity out is not what was expected, found " & std_logic'image(calc_parity(ext_out.payload))
+            & " but expected " & std_logic'image(calc_parity(correct_data))  severity error;
+      fail("Parity out");
+    end if;
+  end procedure;
+
+  component socbridge_driver is
+    port(
+      clk     : in std_logic;
+      rst     : in std_logic;
+      cmd     : in command_t;
+      address : in std_logic_vector(31 downto 0);
+      cmd_size: in positive;
+      ext_in  : in ext_socbridge_in_t;
+      ext_out : out ext_socbridge_out_t;
+      int_in  : out int_socbridge_in_t;
+      int_out : in int_socbridge_out_t
+    );
+  end component socbridge_driver;
+
+begin
+  socbridge_driver_inst: entity work.socbridge_driver
+   port map(
+      clk => clk,
+      rst => rst,
+      cmd => cmd,
+      address => address,
+      cmd_size => cmd_size,
+      ext_in => ext_in,
+      ext_out => ext_out,
+      int_in => int_in,
+      int_out => int_out
+  );
+
+  ext_in.control(1) <= clk;
+  real_clk_proc: process
+  begin
+    for x in 0 to SIMULATION_CYCLE_COUNT*2 loop
+      clk <= not clk;
+      wait for CLK_PERIOD / 2;
+    end loop;
+    wait;
+  end process real_clk_proc;
+  
+  verify_clk: process
+  variable last_clk : std_logic;
+  begin
+    wait for CLK_PERIOD / 2;
+    for x in 0 to SIMULATION_CYCLE_COUNT loop
+      if last_clk = ext_out.control(1) then
+        report "Secondary side clk not correct." severity error;
+      end if;
+      last_clk := ext_out.control(1);
+      wait for CLK_PERIOD;
+    end loop;
+    wait;
+  end process verify_clk;
+
+  verify_out_signals: process
+  variable curr_parity : std_logic;
+  begin
+    wait for CLK_PERIOD / 2;
+    for x in 0 to SIMULATION_CYCLE_COUNT loop
+      check_data_out(expected_out);
+      check_parity(expected_out);
+      wait for CLK_PERIOD;
+    end loop;
+    wait;
+  end process verify_out_signals;
+
+  verify_signals : process
+  variable nsv: boolean;
+  begin
+    expected_out <= "00000000";
+    wait for 3 * CLK_PERIOD;
+    wait for CLK_PERIOD / 3;
+    expected_out <= "00000000";
+    check_next_state(IDLE);
+    wait for CLK_PERIOD /4;
+    check_next_state(TX_HEADER);
+    wait for CLK_PERIOD * 3 / 4;
+    expected_out <= get_cmd_bits(WRITE) & get_size_bits_sim(2);
+    check_next_state(TX_BODY);
+    wait for CLK_PERIOD;
+    expected_out <= "00000001";
+    check_next_state(TX_BODY);
+    wait for CLK_PERIOD;
+    expected_out <= "00000010";
+    check_next_state(TX_ACK);
+    wait for CLK_PERIOD;
+    expected_out <= "00000000";
+    check_next_state(TX_ACK);
+    wait for CLK_PERIOD;
+    check_next_state(IDLE);
+    wait for CLK_PERIOD * 6;
+    expected_out <= "00000000";
+    check_next_state(IDLE);
+    wait for CLK_PERIOD /4;
+    check_next_state(TX_HEADER);
+    wait for CLK_PERIOD * 3 / 4;
+    expected_out <= get_cmd_bits(WRITE_ADD) & get_size_bits(2);
+    check_next_state(ADDR1);
+    wait for CLK_PERIOD;
+    expected_out <= x"FA";
+    check_next_state(ADDR2);
+    wait for CLK_PERIOD;
+    expected_out <= x"A0";
+    check_next_state(ADDR3);
+    wait for CLK_PERIOD;
+    expected_out <= x"0F";
+    check_next_state(ADDR4);
+    wait for CLK_PERIOD;
+    expected_out <= x"FA";
+    check_next_state(TX_BODY);
+    wait for CLK_PERIOD;
+    expected_out <= "00000100";
+    check_next_state(TX_BODY);
+    wait for CLK_PERIOD;
+    expected_out <= "00001000";
+    check_next_state(TX_ACK);
+    wait for CLK_PERIOD;
+    expected_out <= "00000000";
+    check_next_state(TX_ACK);
+    wait for CLK_PERIOD;
+    expected_out <= "00000000";
+    check_next_state(IDLE);
+    wait for CLK_PERIOD * 2;
+    wait for CLK_PERIOD /4;
+    check_next_state(RX_HEADER);
+    wait for CLK_PERIOD * 3 / 4;
+    expected_out <= get_cmd_bits(READ) & get_size_bits(2);
+    check_next_state(RX_RESPONSE);
+    wait for CLK_PERIOD;
+    expected_out <= "00000000";
+    check_next_state(RX_RESPONSE);
+    wait for CLK_PERIOD;
+    wait for CLK_PERIOD / 4;
+    check_next_state(RX_BODY_NO_OUT);
+    wait for CLK_PERIOD * 3 /4;
+    check_next_state(RX_BODY);
+    wait for CLK_PERIOD;
+    check_next_state(RX_BODY);
+    wait for CLK_PERIOD;
+    check_next_state(IDLE);
+    wait for CLK_PERIOD * 5;
+    wait for CLK_PERIOD /4;
+    check_next_state(RX_HEADER);
+    wait for CLK_PERIOD * 3 / 4;
+    expected_out <= get_cmd_bits(READ_ADD) & get_size_bits(2);
+    check_next_state(ADDR1);
+    wait for CLK_PERIOD;
+    expected_out <= x"FA";
+    check_next_state(ADDR2);
+    wait for CLK_PERIOD;
+    expected_out <= x"A0";
+    check_next_state(ADDR3);
+    wait for CLK_PERIOD;
+    expected_out <= x"0F";
+    check_next_state(ADDR4);
+    wait for CLK_PERIOD;
+    expected_out <= x"FA";
+    check_next_state(RX_RESPONSE);
+    wait for CLK_PERIOD;
+    expected_out <= "00000000";
+    check_next_state(RX_RESPONSE);
+    wait for CLK_PERIOD;
+    wait for CLK_PERIOD / 4;
+    check_next_state(RX_BODY_NO_OUT);
+    wait for CLK_PERIOD * 3 /4;
+    check_next_state(RX_BODY);
+    wait for CLK_PERIOD;
+    check_next_state(RX_BODY);
+    wait for CLK_PERIOD;
+    check_next_state(IDLE);
+    wait;
+  end process verify_signals;
+
+  command_stimulus: process
+  begin
+    cmd <= NO_OP;
+    cmd_size <= 2;
+    wait for 3*CLK_PERIOD;
+    wait for CLK_PERIOD / 2;
+    cmd <= WRITE;
+    wait for CLK_PERIOD;
+    cmd <= NO_OP; 
+    wait for CLK_PERIOD * 10;
+    cmd <= WRITE_ADD;
+    address <= x"FA0FA0FA";
+    wait for CLK_PERIOD;
+    cmd <= NO_OP; 
+    address <= (others => '0');
+    wait for CLK_PERIOD * 10;
+    cmd <= READ;
+    wait for CLK_PERIOD;
+    cmd <= NO_OP; 
+    wait for CLK_PERIOD * 10;
+    cmd <= READ_ADD;
+    address <= x"FA0FA0FA";
+    wait for CLK_PERIOD;
+    cmd <= NO_OP; 
+    address <= (others => '0');
+    wait;
+  end process command_stimulus;
+
+  external_stimulus_signal: process(curr_word)
+  begin
+    ext_in.payload <= curr_word;
+    ext_in.control(0) <= calc_parity(curr_word);
+  end process external_stimulus_signal;
+
+  external_stimulus: process
+  begin
+    rst <= '0';
+    wait for CLK_PERIOD / 1000;
+    rst <= '1';
+    curr_word <= "00000000"; 
+    wait for 999 * CLK_PERIOD / 1000;
+    wait for 2 * CLK_PERIOD;
+    rst <= '0';
+    wait for CLK_PERIOD / 2;
+    wait for 4* CLK_PERIOD;
+    curr_word <= "00001001";
+    wait for CLK_PERIOD;
+    curr_word <= "00000000";
+    wait for CLK_PERIOD * 14;
+    curr_word <= "00101001";
+    wait for CLK_PERIOD;
+    curr_word <= "00000000";
+    wait for CLK_PERIOD*5;
+    curr_word <= "01000001";
+    wait for CLK_PERIOD;
+    curr_word <= "10000000";
+    wait for CLK_PERIOD;
+    curr_word <= "01000000";
+    wait for CLK_PERIOD;
+    curr_word <= "00000000";
+    wait for CLK_PERIOD*12;
+    curr_word <= "01100001";
+    wait for CLK_PERIOD;
+    curr_word <= "00100000";
+    wait for CLK_PERIOD;
+    curr_word <= "00010000";
+    wait for CLK_PERIOD;
+    curr_word <= "00000000";
+
+
+    wait;
+  end process external_stimulus;
+
+  internal_stimulus: process
+  begin
+    int_out.is_full_in <= '0';
+    int_out.write_enable_out <= '0';
+    wait for 3 * CLK_PERIOD;
+    -- stimulus goes here
+    int_out.write_enable_out <= '1';
+    int_out.payload <= "00000001";
+    wait until rising_edge(clk) and int_in.is_full_out = '0';
+    wait until falling_edge(clk);
+    int_out.payload <= "00000010";
+    wait until rising_edge(clk) and int_in.is_full_out = '0';
+    wait until falling_edge(clk);
+    int_out.payload <= "00000100";
+    wait until rising_edge(clk) and int_in.is_full_out = '0';
+    wait until falling_edge(clk);
+    int_out.payload <= "00001000";
+    wait until rising_edge(clk) and int_in.is_full_out = '0';
+    wait until falling_edge(clk);
+    int_out.payload <= "00010000";
+    wait until int_in.is_full_out = '0';
+    wait for CLK_PERIOD/2;
+    wait until rising_edge(clk);
+    wait until rising_edge(clk);
+    int_out.payload <= "00100000";
+    wait until int_in.is_full_out = '0';
+    wait for CLK_PERIOD/2;
+    wait until rising_edge(clk);
+    wait until rising_edge(clk); --- ??? Why all these rising_edge checks?
+    wait;
+  end process internal_stimulus;
+  
+end architecture tb ;

src/socbridge_driver_tb_pkg.vhd

@@ -0,0 +1,127 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use IEEE.MATH_REAL.all;
+library work;
+use work.io_types.all;
+
+
+package socbridge_driver_tb_pkg is
+  subtype command_size_t is integer range 1 to 128;
+
+  type command_t is 
+    (NO_OP, WRITE_ADD, WRITE, READ_ADD, READ, P_ERR);
+
+  type response_t is 
+    (NO_OP, WRITE_ACK, READ_RESPONSE);
+
+  type state_t is
+    (IDLE, ADDR1, ADDR2, ADDR3, ADDR4, 
+     TX_HEADER, TX_BODY, TX_ACK, 
+     RX_HEADER, RX_RESPONSE, RX_BODY_NO_OUT, RX_BODY);
+
+  type ext_protocol_t is record
+    data   : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
+    clk    : std_logic;
+    parity : std_logic;
+  end record ext_protocol_t;
+
+  type state_rec_t is record
+    curr_state: state_t;
+    ext_in_reg, ext_out_reg : ext_protocol_t; 
+    write_stage, read_stage : NATURAL;
+    cmd_reg : command_t;
+    addr_reg : std_logic_vector(31 downto 0);
+  end record state_rec_t;
+  impure function calc_parity(
+    d : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0)
+  ) return std_logic;
+  pure function create_io_type_out_from_ext_protocol(
+  input: ext_protocol_t
+  ) return ext_socbridge_out_t;
+  function to_string ( a: std_logic_vector) return string;
+  pure function get_cmd_bits(command : command_t) return std_logic_vector;
+  pure function get_size_bits(size : command_size_t) return std_logic_vector;
+  pure function get_size_bits_sim(size : command_size_t) return std_logic_vector;
+  --- DEBUG GLOBAL SIGNALS ---
+  -- synthesis translate_off 
+  signal G_next_parity_out : std_logic;
+  signal G_ext_in_rec : ext_protocol_t;
+  signal G_ext_out_data_cmd : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
+  signal G_next_state : state_t;
+  signal G_curr_command : command_t;
+  signal G_curr_command_bits : std_logic_vector(4 downto 0);
+  signal G_curr_response : response_t;
+  signal G_curr_response_bits : std_logic_vector(4 downto 0);
+  signal G_st : state_rec_t;
+  -- synthesis translate_on 
+  
+end package socbridge_driver_tb_pkg;
+
+package body socbridge_driver_tb_pkg is
+  function to_string ( a: std_logic_vector) return string is
+  variable b : string (1 to a'length) := (others => NUL);
+  variable stri : integer := 1; 
+  begin
+      for i in a'range loop
+          b(stri) := std_logic'image(a((i)))(2);
+      stri := stri+1;
+      end loop;
+  return b;
+  end function;
+  
+  impure function calc_parity(
+    d : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0)
+  ) return std_logic is
+  variable parity : std_logic;
+  begin
+    parity := d(0);
+    for x in integer'(1) to d'length - 1 loop
+      parity := parity xor d(x);
+    end loop;
+    return not parity;
+  end function;
+  
+  pure function create_io_type_out_from_ext_protocol(
+    input : ext_protocol_t
+  ) return ext_socbridge_out_t is
+  variable val : ext_socbridge_out_t;
+  begin
+    val.payload:= input.data;
+    val.control(1) := input.clk;
+    val.control(0) := input.parity;
+    return val;
+  end function;
+  pure function get_cmd_bits(command : command_t) 
+    return std_logic_vector is
+  variable val : std_logic_vector(4 downto 0);
+  begin
+    with command select
+      val := "00000" when NO_OP,
+             "10000" when WRITE_ADD,
+             "10100" when WRITE,
+             "11000" when READ_ADD,
+             "11100" when READ,
+             "01001" when P_ERR,      
+             "11111" when others;   
+    return val;
+  end function;
+  
+  
+  pure function get_size_bits(size: command_size_t) 
+    return std_logic_vector is
+  variable val : std_logic_vector(2 downto 0);
+  begin
+    val := std_logic_vector(TO_UNSIGNED(size - 1, 3));
+    return val;
+  end function;
+  pure function get_size_bits_sim(size: command_size_t) 
+    return std_logic_vector is
+  variable pow : integer;
+  variable val : std_logic_vector(2 downto 0);
+  begin
+    pow := integer(CEIL(sqrt(Real(size))));
+    val := std_logic_vector(TO_UNSIGNED(size - 1, 3));
+    return val;
+  end function;
+end package body socbridge_driver_tb_pkg;

topology.md

@@ -0,0 +1,32 @@
+                                                                                                      
+                          +------------------------------------------------------+                 +---------------                
+                          |                                                      |                 |                
+                          |  +-----------------+                                 |                 |               
+  *From host*             |  | Instruction     |         G A N I M E D E         |                 |               
+ --------------------------->| queue +         |                                 |                 |  IP-CORE     
+                          |  | scheduler       |                                 |                 |               
+                          |  +-----------------+                                 |                 |               
+                          |    *DMA control*|                                    |                 |               
+                          |                 |                                    |                 |               
+ +--------+               |   +--------+    |    +-----------------+             |                 |               
+ | Inter- |   data +      |   | Driver |<---+    | Per interface   |             |   data +        |               
+ | face 1 |<=================>|      1 |<===|===>| optimizations   |<=============================>|                                
+ |        |   control     |   |        |    |    | (generic)       |             |   control       |                                
+ +--------+               |   +--------+    |    +-----------------+             |                 |                                
+                          |                 |                                    |                 |                                
+ +--------+               |   +--------+    |    +-----------------+             |                 |                                
+ | Inter- |   data +      |   | Driver |<---+    | Per interface   |             |   data +        |                                
+ | face 2 |<=================>|      2 |<===|===>| optimizations   |<=============================>|                                
+ |        |   control     |   |        |    |    | (generic)       |             |   control       |                                
+ +--------+               |   +--------+    |    +-----------------+             |                 |                                
+    ... ... ... ... ... ... ... ... ...  ...|... . ... ... . ... ...... . ... ...    . ... .       |                                
+ +--------+               |   +--------+    |    +-----------------+             |                 |                                
+ | Inter- |   data +      |   | Driver |<---+    | Per interface   |             |   data +        |                                
+ | face n |<=================>|      n |<=======>| optimizations   |<=============================>|                                
+ |        |   control     |   |        |         | (generic)       |             |   control       |                         
+ +--------+               |   +--------+         +-----------------+             |                 |                                   
+                          |                                                      |                 |               
+                          +------------------------------------------------------+                 +---------------               
+
+
+This wont be the first version, but the finished version might look something like this.