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9de6920910
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Added some signal assignments to testbench
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2025-03-10 12:01:15 +01:00 |
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10da15a2e3
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Fixed typing and added translator module to driver (facilitate multi message action) YES
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2025-03-07 16:58:08 +01:00 |
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ad3314bb25
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Boilerplate for control unit and socbridge driver testbench
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2025-03-07 10:42:13 +01:00 |
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a9f1e0fb37
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vhdl_ls configuration
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2025-03-06 15:38:20 +01:00 |
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cd2c920c48
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remodeled entire project to use VHDL libraries
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2025-03-06 14:25:22 +01:00 |
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0ebc9bec9b
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Adjusted io types for communication between control unit and driver. Also started testbench
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2025-03-05 17:06:01 +01:00 |
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2be506209c
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Made instruction a byte instead of a bit
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2025-03-05 17:04:53 +01:00 |
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7a24dc8feb
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Control unit tested and seems to work for the requirements of the basic version
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2025-03-05 17:04:53 +01:00 |
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4c4d62554f
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testbench works
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2025-03-05 17:04:53 +01:00 |
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968acd4e3a
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testbench debgging
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2025-03-05 17:04:53 +01:00 |
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e7b4772223
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testbench almost done, needs debugging
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2025-03-05 17:04:53 +01:00 |
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933e5b66bc
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started working on control unit testbench
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2025-03-05 17:04:53 +01:00 |
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848eaf4c7a
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Started work on control functionality, not tested
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2025-03-05 17:04:53 +01:00 |
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8b0ec9a856
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Started working on io for control unit
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2025-03-05 17:04:53 +01:00 |
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c522997e79
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added support for reads with and without addresses
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2025-03-05 17:04:53 +01:00 |
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a5c9190e2d
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added support for multi word addressable writes
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2025-03-05 17:04:53 +01:00 |
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547ff21a53
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in progress of adding addressing for write command
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2025-03-05 17:04:53 +01:00 |
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2149c1ec68
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added support for multi word writes
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2025-03-05 17:04:53 +01:00 |
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dd7683139c
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improved testbench and removed unnecessary delay caused by 2PM
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2025-03-05 17:04:53 +01:00 |
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eb1bb5d328
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added socbrdige driver tb gtkwave config
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2025-03-05 17:04:53 +01:00 |
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6e3e7deb5e
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At least i know what the problem is...
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2025-03-05 17:04:53 +01:00 |
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d7638c64cd
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begun work on output logic based on state
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2025-03-05 17:04:53 +01:00 |
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52b3b6a7ca
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cleaned up the code in accordance with the two process method
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2025-03-05 17:04:53 +01:00 |
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147d9e4d7b
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added next_state concurrent assignment
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2025-03-05 17:04:53 +01:00 |
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12897f0ae2
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made socbridge driver testbench and continued development on the driver
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2025-03-05 17:04:53 +01:00 |
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cde67ccba1
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inital work on the example socbridge driver
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2025-03-05 17:04:53 +01:00 |
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e87c54d4ef
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added initial driver file
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2025-03-05 17:04:53 +01:00 |
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c6d138b31f
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fixed typing issue for driver definition and added fifo control signals to interface record
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2025-03-05 17:04:53 +01:00 |
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0c36129540
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added more template stuff to ganimede
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2025-03-05 17:04:53 +01:00 |
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895b0242a3
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began working on ganimede template. Unconstrained types are no longer needed
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2025-03-05 17:04:53 +01:00 |
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c3ccfd03ba
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example library package assuming vhdl08. Can be chagned to older ver if needed
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2025-02-17 14:10:58 +01:00 |
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327ce30d16
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added initial test of types needed for ganimede IO
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2025-02-17 14:10:58 +01:00 |
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