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554e3cadab
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buffer probably done but untested, need to rework ganimede toplevel
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2025-04-15 18:06:34 +02:00 |
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56ab5e090a
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minor fixes
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2025-04-15 15:18:00 +02:00 |
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44018d5827
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Started work on fifo buffer
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2025-04-10 16:14:16 +02:00 |
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fccf2dbba3
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PRIMITIVE SUCCESS: made ganimede work in simulation (only 4 byte r/w to ganimede)
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2025-04-09 15:24:55 +02:00 |
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b56ce3a590
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Added prefix "gan_" to all libraries
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2025-04-08 16:20:19 +02:00 |
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5913fc8764
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Restored gtkwave file for socbridge driver testbench
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2025-04-08 14:59:33 +02:00 |
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3fe4b9cedd
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Fixed some bugs and made manager compatible with byte addressing
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2025-04-08 14:59:33 +02:00 |
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f46fde4333
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merged manager and ganimede-rework
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2025-04-08 14:57:18 +02:00 |
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11b42f3211
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Renamed some types
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2025-04-08 14:52:43 +02:00 |
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1b2c7600e6
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first version of management unit done
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2025-04-08 14:52:43 +02:00 |
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2b85765e1f
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made ganimede synthesizable
v1.0.0
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2025-04-07 12:21:20 +02:00 |
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31f0c45f2b
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socbridge fully works with existing socbridge
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2025-04-07 11:24:51 +02:00 |
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abbe417dd3
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added most functionality for answering to commands from external socbridge
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2025-04-04 17:51:46 +02:00 |
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3cf9a13019
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Updated driver with split FSMs, DMA from socbridge works
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2025-04-04 16:48:26 +02:00 |
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842d8b2305
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fixed imports for socbridge
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2025-04-04 16:47:53 +02:00 |
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0747cbfdc9
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made some progress on reformatting socbridge driver
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2025-04-03 17:13:01 +02:00 |
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ffa2ee768c
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added grlib support (socbridge needs to be recompiled)
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2025-04-03 16:14:26 +02:00 |
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c6c5d2d7fc
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RX FSM almost done
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2025-04-03 12:23:51 +02:00 |
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b3a2c4e34a
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Rough outline of new FSMs probably done. All remaining work is hopefully covered by TODOs
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2025-04-02 17:26:51 +02:00 |
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421ed1c006
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Continued work on updating FSMs in SoCBridge-driver
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2025-04-02 16:13:00 +02:00 |
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b09ab5f1ad
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Started reworking socbridge driver
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2025-04-01 17:04:29 +02:00 |
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d739518596
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Added synthesis artifact folder to gitignore
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2025-03-31 11:12:59 +02:00 |
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678afc4bd9
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testbench might work but ghdl broke so could not test
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2025-03-17 12:16:20 +01:00 |
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88dcd19a47
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Refactored controller types to support multiple drivers. Also started ganimede tb
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2025-03-14 17:01:15 +01:00 |
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10d519301e
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Started working on implementing units in top level
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2025-03-13 17:20:28 +01:00 |
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f7f1cedcde
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Merge pull request 'ganimede-toplevel-template' (#13) from ganimede-toplevel-template into main
Reviewed-on: #13
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2025-03-13 16:41:18 +01:00 |
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0a58811b76
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Merge pull request 'ganimede-merge-control-driver' (#12) from ganimede-merge-control-driver into ganimede-toplevel-template
Reviewed-on: #12
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2025-03-13 16:40:45 +01:00 |
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c3d3cef7c9
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Refactoring done
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2025-03-13 16:28:39 +01:00 |
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695745c198
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continued refatctoring. Still not done
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2025-03-12 16:45:44 +01:00 |
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dba8b1a86d
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started refactoring signal names
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2025-03-12 16:05:50 +01:00 |
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9979b7b6dd
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tested, fixed and verified multimessage packet reads
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2025-03-11 15:34:48 +01:00 |
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c96300f6fc
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tested and fixed socbridge for multimessage packets
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2025-03-11 15:10:21 +01:00 |
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82278e77cf
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fixed data not coming through. writes were problematic in tb, reads in socbridge
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2025-03-11 14:55:25 +01:00 |
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4c4a651ee7
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testbench working, all functionality not working
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2025-03-10 17:19:02 +01:00 |
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eb574cf2b8
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Socbridge and controller testbench progress
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2025-03-10 15:08:11 +01:00 |
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9de6920910
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Added some signal assignments to testbench
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2025-03-10 12:01:15 +01:00 |
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10da15a2e3
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Fixed typing and added translator module to driver (facilitate multi message action) YES
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2025-03-07 16:58:08 +01:00 |
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ad3314bb25
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Boilerplate for control unit and socbridge driver testbench
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2025-03-07 10:42:13 +01:00 |
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a9f1e0fb37
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vhdl_ls configuration
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2025-03-06 15:38:20 +01:00 |
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6baa2fd002
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Gantry include paths are now relative
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2025-03-06 15:24:37 +01:00 |
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cd2c920c48
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remodeled entire project to use VHDL libraries
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2025-03-06 14:25:22 +01:00 |
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0ebc9bec9b
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Adjusted io types for communication between control unit and driver. Also started testbench
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2025-03-05 17:06:01 +01:00 |
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2be506209c
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Made instruction a byte instead of a bit
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2025-03-05 17:04:53 +01:00 |
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7a24dc8feb
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Control unit tested and seems to work for the requirements of the basic version
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2025-03-05 17:04:53 +01:00 |
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4c4d62554f
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testbench works
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2025-03-05 17:04:53 +01:00 |
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968acd4e3a
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testbench debgging
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2025-03-05 17:04:53 +01:00 |
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e7b4772223
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testbench almost done, needs debugging
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2025-03-05 17:04:53 +01:00 |
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933e5b66bc
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started working on control unit testbench
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2025-03-05 17:04:53 +01:00 |
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848eaf4c7a
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Started work on control functionality, not tested
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2025-03-05 17:04:53 +01:00 |
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8b0ec9a856
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Started working on io for control unit
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2025-03-05 17:04:53 +01:00 |
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